# US 10,483,043 B2 · Apparatuses, multi-chip modules and capacitive chips

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- Number: US 10,483,043 B2
- Document ID: US10483043B2
- Status: Granted
- Kind: B2
- Application number: 16/439,036
- Filed: 2019-06-12
- Published: 2019-09-26
- Granted: 2019-11-19
- Earliest claimed: 2016-01-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fred D. Fishburn
- Web page: https://patentgrep.com/patent/US10483043B2

## CPC

- H01G 4/385: {Single unit multiple capacitors, e.g. dual capacitor in one coil}
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)}
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H05K 1/162: {incorporating printed capacitors}
- H10D 1/00: Resistors, capacitors or inductors
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H01G 4/40: Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
- H05K 2201/09763: Printed component having superposed conductors, but integrated in one circuit layer
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/00: Package configurations
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

## Claims

### Claim 1

An apparatus, comprising:
a capacitive chip electrically connected with an integrated circuit chip; the capacitive chip comprising capacitive units, and comprising at least four of the capacitive units per square millimeter, the individual capacitive units each comprising:
layers in a capacitor stack, the layers being alternating electrode layers and dielectric layers; the capacitor stack extending across an undulating topography having elevational offsets of from about 30 microns to about 100 microns; the electrode layers comprising one or more metals; the dielectric layers comprising one or more oxides; and
the capacitor stack comprising at least 10 of the layers.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein all of the capacitive units of said plurality are substantially identical to one another in capacitance.

### Claim 3 (depends on 1)

The apparatus of claim 1 wherein at least one of the capacitive units of said plurality has a substantially different capacitance than another of the capacitive units of said plurality.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein the capacitor stacks comprise at least 30 of the layers.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein the capacitor stacks comprise at least 50 of the layers.

### Claim 6

A multi-chip module, comprising:
a power distribution component configured to provide a power supply voltage;
a capacitive chip electrically coupled to the power distribution component and comprising capacitive units;
an integrated circuit chip electrically coupled to at least one of the capacitive chip and the power distribution component, the integrated circuit chip comprising a controller configured to provide memory commands to a memory; and
wherein individual of the capacitive units of the capacitive chip comprise:
layers in a capacitor stack, the layers being alternating electrode layers and dielectric layers; the capacitor stack extending across an undulating topography; the undulating topography comprising trenches having depths within a range of from about 30 microns to about 100 microns and having bottom widths of at least about 1 micrometer; the electrode layers comprising one or more metals; the dielectric layers comprising one or more oxides; and
the capacitor stack comprising at least 10 of the layers.

### Claim 7 (depends on 6)

The multi-chip module of claim 6 wherein the integrated circuit chip is electrically coupled to the capacitive chip.

### Claim 8 (depends on 6)

The multi-chip module of claim 6 wherein the capacitor stacks comprise at least 30 of the layers.

### Claim 9 (depends on 6)

The multi-chip module of claim 6 wherein the capacitor stacks comprise at least 50 of the layers.

### Claim 10 (depends on 6)

The multi-chip module of claim 6 wherein the trenches extend into a semiconductor substrate.

### Claim 11 (depends on 6)

The multi-chip module of claim 6 wherein all of the capacitive units of the capacitive chip are substantially identical to one another in capacitance.

### Claim 12 (depends on 6)

The multi-chip module of claim 6 wherein at least one of the capacitive units of the capacitive chip has a substantially different capacitance than another of the capacitive units of the capacitive chip.