# US 10,482,982 B2 · Semiconductor device and operating method of the semiconductor device

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- Number: US 10,482,982 B2
- Document ID: US10482982B2
- Status: Granted
- Kind: B2
- Application number: 16/058,677
- Filed: 2018-08-08
- Published: 2019-06-27
- Granted: 2019-11-19
- Earliest claimed: 2017-12-26
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Youl Lee
- Web page: https://patentgrep.com/patent/US10482982B2

## CPC

- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5622: Concurrent multilevel programming of more than one cell
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a method for operating a semiconductor device, the method may include: sorting program states of a memory cell that stores multi-bit data into a plurality of groups; applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups; applying a program voltage to a selected word line corresponding to the selected group; verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state; applying an inhibition voltage to bit lines coupled to programmed memory cells; and selecting a next group to be programmed until the plurality of groups are programmed.

## Claims

### Claim 1

A method for operating a semiconductor device, the method comprising:
sorting program states of a memory cell that stores multi-bit data into a plurality of groups;
applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups;
applying a program voltage to a selected word line corresponding to the selected group;
verifying whether each of a plurality of selected memory cells corresponding to the selected word line is programmed to a respective target program state;
applying an inhibition voltage to bit lines coupled to programmed memory cells; and
selecting a next group to be programmed until the plurality of groups are programmed.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the bias voltages to be applied to the bit lines is determined according to a logical value of the multi-bit data to be programmed in each of the memory cells.

### Claim 3 (depends on 1)

The method of claim 1, wherein differences between bias voltages applied to bit lines corresponding to the next group are equal to the differences between bias voltages applied to the bit lines corresponding to the selected group.

### Claim 4 (depends on 1)

The method of claim 1, wherein the program voltage is applied to the selected word line while different bias voltages are applied to the bit lines corresponding to the selected group, and an inhibition voltage is applied to bit lines corresponding to an unselected group among the plurality of groups.

### Claim 5 (depends on 1)

The method of claim 1, wherein, in the applying of the bias voltages, the greatest bias voltage among the bias voltages applied to the selected bit lines is applied to bit lines corresponding to an unselected group among the plurality of groups.

### Claim 6 (depends on 5)

The method of claim 5, wherein memory cells corresponding to the unselected groups are pre-programmed using a program operation of the selected group.

### Claim 7 (depends on 6)

The method of claim 6, wherein, when a pre-programmed group is selected, a program voltage is applied to a selected word line while different bias voltages are applied to bit lines corresponding to the selected pre-programmed group, so that a main program operation is performed on the pre-programmed memory cells.

### Claim 8 (depends on 6)

The method of claim 6, wherein the pre-programmed memory cells are verified using a verify voltage of a program state having the least level among program states belonging to the selected group.

### Claim 9 (depends on 5)

The method of claim 5, wherein an inhibition voltage is applied to bit lines corresponding to a group adjacent to the selected group among the unselected groups.

### Claim 10 (depends on 1)

The method of claim 1, wherein a greater program voltage than the previously used program voltage is applied to the next group to be programmed.

### Claim 11

A method for operating a semiconductor device, the method comprising:
receiving multi-bit data to be programmed in each of a plurality of memory cells;
applying different bias voltages to bit lines corresponding to selected memory cells among the plurality of memory cells according to a logical value of the multi-bit data;
applying a program voltage to a selected word line corresponding to the selected memory cells; and
verifying whether each of the selected memory cells corresponding to the selected word line is programmed to a respective target program state.

### Claim 12 (depends on 11)

The method of claim 11, further comprising applying an inhibition voltage to bit lines corresponding to programmed memory cells.

### Claim 13

A semiconductor device comprising:
memory cells each configured to store multi-bit data;
bit lines corresponding to the respective memory cells;
word lines electrically coupled to gate electrodes of the memory cells; and
a control logic configured to sort program states of a memory cell that store multi-bit data into a plurality of groups, control application of different bias voltages to bit lines corresponding to a selected group among the plurality of groups, control application of a program voltage to a selected word line corresponding to the selected group, and verify whether each of a plurality of selected memory cells corresponding to the selected word line is programmed to a respective target program state.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the control logic determines each of the bias voltages to be applied to the bit lines according to a logical value of the multi-bit data to be programmed in each of the memory cells.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the control logic controls application of an inhibition voltage to bit lines corresponding to programmed memory cells, and selects a next group to be programmed.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein, when different bias voltages are applied to the bit lines corresponding to the selected group, the control logic controls application of an inhibition voltage to bit lines corresponding to an unselected group among the plurality of groups.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein, when different bias voltages are applied to the bit lines corresponding to the selected group, the control logic controls application of the greatest bias voltage among the bias voltages applied to the bit lines corresponding to the selected group to bit lines corresponding to an unselected group among the plurality of groups.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein memory cells corresponding to the unselected groups are pre-programmed using a program operation of the selected group.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein, when a pre-programmed group is selected, a program voltage is applied to a selected word line while different bias voltages are applied to bit lines corresponding to the selected pre-programmed group, so that a main program operation is performed on the pre-programmed memory cells.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the pre-programmed memory cells are verified using a verify voltage of a program state having the least level among program states belonging to the selected group.