# US 10,482,981 B2 · Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors

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- Number: US 10,482,981 B2
- Document ID: US10482981B2
- Status: Granted
- Kind: B2
- Application number: 15/900,093
- Filed: 2018-02-20
- Published: 2019-08-22
- Granted: 2019-11-19
- Earliest claimed: 2018-02-20
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Ching-Huang Lu; Vinh Diep
- Web page: https://patentgrep.com/patent/US10482981B2

## CPC

- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.

## Claims

### Claim 1

An apparatus, comprising:
a set of connected memory cells comprising a data memory cell adjacent to one or more dummy memory cells, the data memory cell comprising a control gate and the one or more dummy memory cells comprising a dummy memory cell positioned adjacent to a select gate transistor; and
a refresh circuit configured to repeatedly increase a voltage at the control gate to keep the voltage at the control gate higher than a voltage of a control gate of the dummy memory cell positioned adjacent to the select gate transistor.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
the refresh circuit is configured to increase the voltage of the control gate of the data memory cell in response to expiration of a timer.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein:
the set of connected memory cells is in a block; and
a period of the timer is a decreasing function of a number of program-erase cycles of the block.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the refresh circuit, to repeatedly increase the voltage of the control gate of the data memory cell, is configured to repeatedly apply a voltage pulse to the control gate of the data memory cell followed by floating the voltage of the control gate of the data memory cell; and
the refresh circuit is configured to float the voltage of the control gate of the dummy memory cell positioned adjacent to the select gate transistor during the floating of the voltage of the control gate of the data memory cell.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein:
the refresh circuit is configured to ground the voltage of the control gate of the dummy memory cell positioned adjacent to the select gate transistor during the application of the voltage pulse to the control gate of the data memory cell.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein:
the refresh circuit is configured to set the voltage of the control gate of the dummy memory cell positioned adjacent to the select gate transistor at a level which is below a level of the voltage pulse which is applied to the control gate of the data memory cell, during the application of the voltage pulse to the control gate of the data memory cell.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising:
a voltage driver connected to a control gate of the data memory cell via a pass transistor, wherein the refresh circuit, to repeatedly increase the voltage of the control gate of the data memory cell, is configured to repeatedly control the voltage driver to output a positive voltage while the pass transistor is turned on, followed by turning off the pass transistor while the voltage driver outputs the positive voltage.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein:
the repeated increase of the voltage of the control gate of the data memory cell occurs without a repeated increase of the voltage of the control gate of the dummy memory cell positioned adjacent to the select gate transistor.

### Claim 9 (depends on 4)

The apparatus of claim 4, wherein the set of connected memory cells is in a selected block, further comprising:
a set of connected memory cells in an unselected block, the set of connected memory cells in the unselected block comprising a data memory cell, a dummy memory cell and a select gate transistor adjacent to the dummy memory cell in the unselected block; and
a voltage driver configured to apply a positive voltage to a control gate of the data memory cell in the unselected block, the positive voltage is less than a magnitude of the voltage pulse, and a ground voltage to a control gate of the dummy memory cell in the unselected block, when the refresh circuit applies the voltage pulse to the control gate of the data memory cell in the selected block.

### Claim 10 (depends on 9)

The apparatus of claim 9, further comprising:
a first set of pass transistors connected to the control gate of the data memory cell in the selected block and the control gate of the dummy memory cell positioned adjacent to the select gate transistor in the selected block; and
a second set of pass transistors connected to the control gate of the data memory cell in the unselected block and the control gate of the dummy memory cell in the unselected block, wherein control gates of the first set of pass transistors are connected to control gates of the second set of pass transistors.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein:
the set of connected memory cells is in a selected block; and
the refresh circuit is configured to repeatedly increase the voltage of the control gate of the data memory cell during an idle time of the selected block when no program, read or erase operation is being performed in the selected block.

### Claim 12

A method, comprising:
sensing a data memory cell in a set of connected memory cells in a selected block of a memory device, the set of connected memory cells also comprising a dummy memory cell, the dummy memory cell positioned adjacent to a select gate transistor, the memory device also comprising a set of connected memory cells in an unselected block, the set of connected memory cells in the unselected block comprising a data memory cell and a dummy memory cell, the dummy memory cell in the unselected block positioned adjacent to a select gate transistor in the unselected block; and
during the sensing of the data memory cell in the selected block, applying a positive voltage to a control gate of the data memory cell in the unselected block, and applying a ground voltage to a control gate of the dummy memory cell in the unselected block.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
upon completion of the sensing, setting a timer; and
upon expiration of the timer, concurrently boosting a voltage of a control gate of the data memory cell in the selected block, applying the ground voltage to a control gate of the dummy memory cell in the selected block, applying the positive voltage to the control gate of the data memory cell in the unselected block, and applying the ground voltage to the control gate of the dummy memory cell in the unselected block.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the boosting the voltage of the control gate of the data memory cell in the selected block comprises applying a voltage pulse to the control gate of the data memory cell in the selected block followed by floating the voltage of the control gate of the data memory cell in the selected block; and
the voltage of the control gate of the dummy memory cell in the selected block and the voltage of the control gate of the dummy memory cell in the unselected block are floated during the floating of the voltage of the control gate of the data memory cell in the selected block.

### Claim 15

An apparatus, comprising:
a selected block comprising memory cells, the memory cells arranged in NAND strings and connected to a set of word lines comprising data word lines and a dummy word line;
means for applying a voltage pulse to the data word lines followed by floating of voltages of the data word lines, the applying of the voltage pulse followed by the floating of the voltages occurs repeatedly; and
means for grounding a voltage of the dummy word line during the application of the voltage pulses.

### Claim 16 (depends on 15)

The apparatus of claim 15, further comprising:
an unselected block comprising memory cells, the memory cells are arranged in NAND strings and connected to a set of word lines comprising data word lines and a dummy word line;
means for applying a positive voltage to the data word lines of the unselected block during the applying the voltage pulse to the data word lines of the selected block; and
means for grounding a voltage of the dummy word line of the unselected block during the applying the voltage pulse to the data word lines of the selected block.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein:
the set of word lines comprises a drain side dummy word line and a source side dummy word line; and
the means for grounding alternates between grounding the drain side dummy word line and a source side dummy word line during successive applications of the voltage pulse.

### Claim 18

An apparatus, comprising:
a plurality of NAND strings arranged in a selected block, each NAND string comprising data memory cells connected to data word lines, a dummy memory cell connected to a dummy word line, and a select gate transistor adjacent to the dummy memory cell, wherein voltages of the data word lines and a voltage of the dummy word line decay when no storage operation is being performed in the selected block;
a trigger circuit configured to determine that a condition is met to refresh the voltages of the data word lines; and
maintenance circuitry, the maintenance circuitry, to refresh the voltages of the data word lines, is configured to apply a voltage pulse to the data word lines while grounding the dummy word line, then float the voltage of the data word lines while floating the voltage of the dummy word line.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein:
the maintenance circuitry is configured to repeatedly apply a voltage pulse to the data word lines while grounding the dummy word line.

### Claim 20

A system, comprising:
a controller; and
a memory die connected to the controller, the memory die comprises:
a set of connected memory cells comprising a data memory cell and a dummy memory cell; and
a select gate transistor adjacent to the dummy memory cell, the controller configured to repeatedly increase a voltage of a control gate of the data memory cell while grounding a control gate of the dummy memory cell.

### Claim 21 (depends on 12)

The method of claim 12, wherein:
the positive voltage is greater than a power supply voltage of the memory device and less than a pass voltage.

### Claim 22 (depends on 16)

The apparatus of claim 16, wherein:
the positive voltage is greater than a power supply voltage and less than the voltage pulse.