# US 10,482,980 B2 · Semiconductor device having ring oscillator and method of arranging ring oscillator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,980 B2 - Document ID: US10482980B2 - Status: Granted - Kind: B2 - Application number: 15/946,299 - Filed: 2018-04-05 - Published: 2019-02-28 - Granted: 2019-11-19 - Earliest claimed: 2017-08-31 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Seung Wan Chai - Web page: https://patentgrep.com/patent/US10482980B2 ## CPC - G11C 16/32: Timing circuits - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K 3/0315: {Ring oscillators} - H03K 3/0322: {with differential cells} - H03K 3/35613: {the input circuit having a differential configuration} - H03K 3/356182: {with additional means for controlling the main nodes} - H03K 5/134: with field-effect transistors - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K 19/018528: {with at least one differential stage} - H03K 19/018585: {programmable} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H03K 5/05: by the use of clock signals or other time reference signals - H03K 2005/00195: {using FET's} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current, wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about a square. ## Claims ### Claim 1 A ring oscillator comprising: first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current; and a current control circuit configured to control the magnitude of the sink current, wherein the current control circuit is arranged at a center of a square, and wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about the square. ### Claim 2 (depends on 1) The ring oscillator of claim 1, wherein the first to fourth current-controlled delay circuits are arranged adjacent or at four sides of the square, respectively, each of the first to fourth current-controlled delay circuits outputs a first output signal and a second output signal, the first output signal and the second output signal of the first current-controlled delay circuit are transferred to first and second input nodes of the second current-controlled delay circuit and third and fourth input nodes of the third current-controlled delay circuit, and the first output signal and the second output signal have a phase difference of 180 degrees. ### Claim 3 (depends on 2) The ring oscillator of claim 2, wherein the first output signal of the fourth current-controlled delay circuit and the first output signal of the first current-controlled delay circuit have a phase difference of 45 degrees. ### Claim 4 (depends on 2) The ring oscillator of claim 2, wherein lines for transferring the first output signals and the second output signals output by the first to fourth current-controlled delay circuits have routing loads equal to one another. ### Claim 5 (depends on 1) The ring oscillator of claim 1, wherein a period of a clock signal output from the ring oscillator is shortened as the sink current increases. ### Claim 6 (depends on 1) The ring oscillator of claim 1, further comprising first to fourth differential input single output converters respectively coupled to the first to fourth current-controlled delay circuits, wherein the first to fourth differential input single output converters are arranged adjacent or at four vertexes of the square, respectively. ### Claim 7 (depends on 6) The ring oscillator of claim 6, wherein the first differential input single output converter is arranged adjacent or at one vertex of a first side of the square, adjacent or at which the first current-controlled delay circuit is arranged. ### Claim 8 (depends on 7) The ring oscillator of claim 7, wherein each of the first to fourth differential input single output converters receives a first input signal and a second input signal, which are transferred from each of the first to fourth current-controlled delay circuit, and lines for transferring the first input signal and the second input signal, which are input from each of the first to fourth differential input single output converters, have routing loads equal to one another. ### Claim 9 (depends on 7) The ring oscillator of claim 7, wherein the current control circuit is commonly coupled to the first to fourth current-controlled delay circuits. ### Claim 10 (depends on 7) The ring oscillator of claim 7, wherein each of the first to fourth differential input single output converters includes a pre-amplifier and an output-amplifier, wherein two output nodes of the pre-amplifier are coupled to two input nodes of the output-amplifier. ### Claim 11 (depends on 1) The ring oscillator of claim 1, wherein each of the first to fourth current-controlled delay circuits includes first and second PMOS transistors commonly coupled to a power voltage and first and second NMOS transistors commonly coupled to a current control node, wherein the first PMOS transistor and the second PMOS transistor are cross-coupled to each other. ### Claim 12 A semiconductor device comprising: a ring oscillator configured to generate a clock signal, wherein the ring oscillator includes: first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current; a current control circuit configured to determine the magnitude of the sink current and arranged at a center of a square; and first to fourth differential input single output converters respectively coupled to the first to fourth current-controlled delay circuits, wherein the first to fourth differential input single output converters are arranged adjacent or at four sides of the square, respectively. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first to fourth differential input single output converters are arranged adjacent or at four vertexes of the square, respectively. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein a period of the clock signal is determined by the delay time. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the first to fourth current-controlled delay circuits generate first to eighth signals having different phases, and phase differences between the first to eighth signals are generated by 45 degrees. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein lines for transferring output signals of the first to fourth current-controlled delay circuits have routing loads equal to one another. ### Claim 17 A memory device comprising: a ring oscillator configured to generate a first clock signal; a frequency divider configured to output a second clock signal in response to the first clock signal; and an input/output circuit configured to perform a data input/output operation in synchronization with the second clock signal, wherein the ring oscillator includes: first to fourth current-controlled delay circuits; first to fourth differential input single output converters respectively coupled to the first to fourth current-controlled delay circuits; and a current control circuit coupled to each of the first to fourth current-controlled delay circuits wherein the current control circuit is arranged adjacent or at a center of a square, wherein the first to fourth current-controlled delay circuits are arranged adjacent or at four sides of the square, respectively, and wherein the first to fourth differential input single output converters are arranged adjacent or at four vertexes of the square, respectively. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the first clock signal has a period that is two times larger than that of the second clock signal.