# US 10,482,979 B1 · Capacitive voltage modifier for power management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,979 B1 - Document ID: US10482979B1 - Status: Granted - Kind: B1 - Application number: 16/119,715 - Filed: 2018-08-31 - Granted: 2019-11-19 - Earliest claimed: 2018-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Matthew D. Rowley; Dustin J. Carter - Web page: https://patentgrep.com/patent/US10482979B1 ## CPC - G11C 16/30: Power supply circuits - G01R 19/16552: {in I.C. power supplies} - G05F 1/462: {as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic} - G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)} - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G11C 5/141: {Battery and back-up supplies} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 16/10: Programming or data input circuits - H02M 3/1582: {Buck-boost converters (H02M3/1584 takes precedence)} - G11C: STATIC STORES (semiconductor memory devices H10B) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage. ## Claims ### Claim 1 A memory sub-system, comprising: a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system, the PMIC configured to output a plurality of voltages for operation of the memory sub-system based on a PMIC supply voltage; and a capacitive voltage modifier (CVM) coupled to the PMIC, the CVM configured to: receive the primary supply voltage of the memory sub-system as an input; and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, wherein the first MPSV is not higher than the uppermost PMIC supply voltage. ### Claim 2 (depends on 1) The memory sub-system of claim 1, wherein the memory sub-system is a solid-state drive (SSD). ### Claim 3 (depends on 1) The memory sub-system of claim 1, further comprising; a backup power component (BPC) coupled to the CVM, the BPC configured to operate as a backup power supply of the memory sub-system; and wherein: the CVM is further configured to provide a second MPSV to charge the BPC; and the second MPSV is not lower than the primary supply voltage of the memory sub-system. ### Claim 4 (depends on 1) The memory sub-system of claim 1, wherein the CVM is further configured to selectably adjust the primary supply voltage to a second MPSV to charge a backup power component via a plurality of parallel-coupled capacitors. ### Claim 5 (depends on 1) The memory sub-system of claim 1, wherein: the CVM is further configured to selectably adjust the primary supply voltage to the first MPSV via a plurality of series-coupled capacitors; and the PMIC is further configured to convert the first MPSV, received from the CVM, to the plurality of voltages for operation of the memory sub-system to be output from the PMIC. ### Claim 6 (depends on 1) The memory sub-system of claim 1, wherein the CVM is further configured to: receive, as the input, a plurality of different primary supply voltages that are higher than the uppermost PMIC supply voltage; and reduce each of the plurality of different primary supply voltages to provide the first MPSV to the PMIC as the PMIC supply voltage. ### Claim 7 (depends on 1) The memory sub-system of claim 1, wherein the CVM is further configured to, based on a status of the primary supply voltage being monitored, provide signals to select between a plurality of connections of a plurality of capacitors of the CVM that enable: output of the first MPSV to the PMIC; and output of a second MPSV to a backup power component; and wherein the first and second MPSVs each have different voltage magnitudes. ### Claim 8 (depends on 1) The memory sub-system of claim 1, further comprising a connector through which the primary supply voltage is received, wherein the CVM is further configured to scale the primary supply voltage by a selectable ratio to provide the first MPSV. ### Claim 9 (depends on 8) The memory sub-system of claim 8, wherein: the CVM is further configured to amplify the primary supply voltage by a selectable amount to a second MPSV; and the selectable amount is determined based, at least partially, on a characteristic of a backup power component. ### Claim 10 (depends on 1) The memory sub-system of claim 1, wherein the PMIC comprises: a first regulator configured to reduce the first MPSV received from the CVM; and a second regulator configured to increase the first MPSV received from the CVM. ### Claim 11 (depends on 1) The memory sub-system of claim 1, wherein: the PMIC is further configured to reduce the first MPSV received from the CVM to a reduced voltage compatible with operation of an array of memory cells of the memory sub-system; the reduced voltage is selectably output from the PMIC for operation of the array; and an amplified voltage, corresponding to a second MPSV, is selectably output from the CVM to charge a backup power component. ### Claim 12 A memory sub-system, comprising: a capacitive voltage modifier (CVM) configured to decrease a primary supply voltage received from a primary power supply (PPS) coupled to the memory sub-system; wherein the decrease is selectably determined to provide a power management integrated circuit (PMIC) supply voltage that is lower than the primary supply voltage and that is compatible with operation of the PMIC. ### Claim 13 (depends on 12) The memory sub-system of claim 12, wherein: the CVM is further configured to increase the primary supply voltage received from the PPS; and the increase is selectably determined, based at least partially on, a characteristic of a backup power component (BPC) coupled via the CVM to the PMIC. ### Claim 14 (depends on 12) The memory sub-system of claim 12, wherein: responsive to the primary supply voltage being lower than a threshold voltage for operation of the memory sub-system, the memory sub-system is configured to provide a backup voltage from the BPC to the CVM; the CVM receives the backup voltage from the BPC, wherein the backup voltage is not lower than the primary supply voltage; the CVM produces a decreased backup voltage for output to the PMIC; and the PMIC converts the decreased backup voltage into a reduced voltage compatible with operation of a memory component. ### Claim 15 (depends on 12) The memory sub-system of claim 12, further comprising: a backup power control component that is part of the CVM and is configured to: determine a particular number of a plurality of capacitors of the CVM to connect to reduce a backup voltage, received from the BPC, to a decreased backup voltage; direct the CVM to connect the particular number of the plurality of capacitors; and direct the CVM to output the decreased backup voltage to the PMIC. ### Claim 16 (depends on 12) The memory sub-system of claim 12, further comprising: a backup power control component that is part of the CVM and is configured to: direct the CVM to increase the primary supply voltage for storage by capacitive storage component (CSC) of the BPC prior to a determination that the PPS provides a primary supply voltage that is lower than a threshold voltage; direct a particular number of a plurality of capacitors of the CVM to connect to increase the primary supply voltage to an increased primary supply voltage, based at least partially on, a characteristic of the CSC; and direct the CVM to output the increased primary supply voltage for storage by the CSC. ### Claim 17 (depends on 12) The memory sub-system of claim 12, wherein: responsive to a determination by a monitoring unit that is part of the CVM that the primary supply voltage is lower than a threshold voltage for operation of the memory sub-system, a connector to the PPS is configured to disconnect the memory sub-system from the PPS; the CVM receives a backup voltage from the BPC that enables performance of a number of operations by a memory component; and the number of operations includes data values stored by the memory component being moved for storage by a number of non-volatile memory cells. ### Claim 18 A method, comprising: receiving a primary supply voltage that is higher than an uppermost supply voltage at which the a power management integrated circuit (PMIC) is configured to operate; and selectably providing a first modified primary supply voltage (MPSV) to the PMIC as a PMIC supply voltage, wherein the first MPSV is not higher than the uppermost supply voltage at which the PMIC is configured to operate. ### Claim 19 (depends on 18) The method of claim 18, further comprising selectably providing the first MPSV to the PMIC by a capacitive voltage modifier (CVM). ### Claim 20 (depends on 18) The method of claim 18, further comprising: selectably providing a second MPSV to a backup power component (BPC) by a capacitive voltage modifier (CVM), wherein the second MPSV is not lower than the primary supply voltage; and charging the BPC via the second MPSV. ### Claim 21 (depends on 18) The method of claim 18, further comprising: responsive to a reduction of the primary supply voltage, providing an output voltage of a backup power component (BPC) to a capacitive voltage modifier (CVM); and modifying the output voltage of the BPC to power the PMIC. ### Claim 22 (depends on 18) The method of claim 18, further comprising selectably reducing the first MPSV, using a voltage converter of the PMIC, to a further reduced voltage compatible with operation of a selected memory component of a solid-state drive. ### Claim 23 (depends on 18) The method of claim 18, further comprising: outputting a backup voltage from a backup power component (BPC) to a capacitive voltage modifier (CVM) responsive to detection of a reduced primary supply voltage; performing, by the CVM, a coarse adjustment on the backup voltage to cause a reduced backup voltage to be within a predetermined range of voltages compatible with operation of the PMIC; and performing, by the PMIC, a fine adjustment on the reduced backup voltage received from the CVM to cause a further reduced voltage to be within a predetermined range of voltages compatible with performance of an operation on a selected array of memory cells on a solid-state drive; and wherein: performing the coarse adjustment includes the predetermined range of voltages compatible with operation of the PMIC being wider than the predetermined range of voltages compatible with operation of the selected array that is caused by the fine adjustment; and performing the fine adjustment includes the values of the further reduced voltages that are compatible with performance of the number of operations on the selected array being less than the values of the reduced backup voltages that are compatible with operation of the PMIC. ### Claim 24 (depends on 18) The method of claim 18, further comprising: configuring a processing device of a solid-state drive (SSD) to receive instructions, from a host separate from the SSD, for performance of an operation on a selected memory component of the SSD and to direct performance of the operation by: a PMIC power control component of a capacitive voltage modifier (CVM) selectably directing the CVM to perform an adjustment on the primary supply voltage to cause the first MPSV to be within a predetermined range of voltages compatible with operation of the PMIC; and a backup power control component of the CVM selectably directing the CVM to perform an adjustment on a backup voltage received from a backup power component to cause a reduced backup voltage to be within a predetermined range of voltages compatible with operation of the PMIC.