# US 10,482,978 B2 · Read voltage optimization method, memory storage device and memory control circuit unit

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- Number: US 10,482,978 B2
- Document ID: US10482978B2
- Status: Granted
- Kind: B2
- Application number: 16/048,366
- Filed: 2018-07-30
- Published: 2019-09-12
- Granted: 2019-11-19
- Earliest claimed: 2018-03-09
- Assignees: Shenzhen EpoStar Electronics Limited CO.
- Applicants: Shenzhen EpoStar Electronics Limited CO.
- Inventors: Yu-Hua Hsiao; Li-Hsun Liu
- Web page: https://patentgrep.com/patent/US10482978B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A decoding method is provided. The method includes selecting a target word line among a plurality of word lines; respectively reading a plurality of target memory cells of the target word-line by using different X read voltage sets to obtain corresponding X Gray code summation sets; calculating a Gray code count summation difference of the Gray code count summations at the same sequence position respectively in N−1 Gray code count summations between every pair of adjacent Gray code summation sets of the X Gray code summation sets, so as to obtain X−1 Gray code count summation difference sets corresponding to all pairs of the Gray code summation sets; and deciding N−1 optimized read voltages from X*(N−1) read voltages belonging to the X read voltage sets according to the X−1 Gray code count summation difference sets.

## Claims

### Claim 1

A decoding method for a storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of word lines, each of the word lines comprises a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different Gray codes, a total number of the Gray codes is N, N is a first predetermined positive integer greater than 2, and the method comprises:
choosing a target word line of the word lines, wherein a plurality of target memory cells of the target word line are programmed;
respectively reading the target memory cells by using different X read voltage sets to obtain corresponding X Gray code summation sets, wherein X is a second predetermined positive integer, the X read voltage sets and the corresponding X Gray code summation sets are arranged based on a first predetermined order, a voltage difference between every pair of adjacent read voltage sets in the X read voltage sets is a first predetermined voltage difference, each of the X read voltage sets has N−1 read voltages arranged based on a second predetermined order, wherein each of the X Gray code summation sets has N−1 Gray code count summations arranged based on the second predetermined order, and a jth Gray code count summation in the N−1 Gray code count summations corresponds to a jth read voltage in the N−1 read voltages, wherein the jth Gray code count summation is calculated by summing up first j Gray code counts among N Gray code counts, wherein the N Gray code counts are calculated by summing up the numbers of a plurality of read bit values classified into the respective Gray codes, wherein the read bit values are obtained by using a corresponding read voltage set to read the target memory cells;
choosing every pair of adjacent Gray code summation sets in the X gray code summation sets based on the first predetermined order, and calculating a Gray code count summation difference of the Gray code count summations at the same sequence position in the respective N−1 Gray code count summations between every pair of adjacent Gray code summation sets based on the second predetermined order, so as to obtain X−1 Gray code count summation difference sets corresponding to all the chosen pairs of the Gray code summation sets, wherein each of the X−1 Gray code count summation difference sets comprises N−1 Gray code count summation differences arranged based on the second predetermined order, and a jth Gray code count summation difference in the N−1 Gray code count summation differences corresponds to the jth read voltage in the N−1 read voltages; and
determining N−1 optimized read voltages corresponding to the second predetermined order from X*(N−1) read voltages belonging to the X read voltage sets based on the N−1 Gray code count summation differences of each of the X−1 Gray code count summation difference sets to form an optimized read voltage set corresponding to the target word line.

### Claim 2 (depends on 1)

The decoding method as claimed in claim 1, further comprising:
performing a quick read voltage screening operation after choosing the target word line of the word lines to determine the X read voltage sets, wherein the quick read voltage screening operation comprises:
reading the target memory cells by using Z read voltage sets to obtain Z Gray code count sets respectively corresponding to the Z read voltage sets, wherein a voltage difference between every pair of adjacent read voltage sets of the Z read voltage sets is a second predetermined voltage difference, a value of Z is less than the second predetermined positive integer, and the second predetermined voltage difference is greater than the first predetermined voltage difference;
obtaining one of the Z read voltage sets as an initial reference read voltage set based on at least one of a first Gray code count and a last Gray code count of each of the Z Gray code count sets and a Gray code count predetermined value; and
determining the X read voltage sets based on the initial reference read voltage sets, a first Gray code count deviation, the second predetermined positive integer, and the first predetermined voltage difference.

### Claim 3 (depends on 1)

The decoding method as claimed in claim 1, wherein values of j include 1 to N−1 based on the second predetermined order, and respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets comprises:
choosing an ith read voltage set of the X read voltage sets, wherein values of i include 1 to X based on the first predetermined order;
respectively reading the target memory cells by using N−1 read voltages of the ith read voltage set to obtain the read bit values corresponding to the ith read voltage set and classified into the Gray codes;
summing up the numbers of the read bit values classified into the respective Gray codes as the N Gray code counts corresponding to the ith read voltage set based on the obtained read bit values corresponding to the ith read voltage set and the Gray codes which the read bit values belong to, wherein the Gray code counts are arranged based on a third predetermined order; and
calculating N−1 Gray code count summations based on the N Gray code counts corresponding to the ith read voltage set and the second predetermined order, and obtaining the N−1 Gray code count summations as an ith Gray code summation set corresponding to the ith read voltage set in the X Gray code summation sets, wherein a value of a jth Gray code count summation in the N−1 Gray code count summations is a summation of the first j Gray code counts.

### Claim 4 (depends on 3)

The decoding method as claimed in claim 3, wherein respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets further comprises:
calculating the N−1 Gray code count summations in each of the X Gray code summation sets based on a formula as follows:
SLi,j=Σk=1jCi,k,∀i∈[1,X],∀j∈[1,N−1]
wherein SLi,j represents the jth Gray code count summation in the ith Gray code summation set corresponding to the ith read voltage set, Ci,k represents a kth Gray code count in the N Gray code counts corresponding to the ith read voltage set, wherein values of k include 1 to N−1 based on the second predetermined order.

### Claim 5 (depends on 1)

The decoding method as claimed in claim 1, wherein choosing the every pair of adjacent Gray code summation sets in the X gray code summation sets based on the first predetermined order and calculating the Gray code count summation difference of the Gray code count summations at the same sequence position in the respective N−1 Gray code count summations between every chosen pair of two Gray code summation sets based on the second predetermined order to obtain the X−1 Gray code count summation difference sets corresponding to all the chosen pairs of the Gray code summation sets comprises:
choosing an ith Gray code summation set and an i+1th Gray code summation set from the X Gray code summation sets; and
calculating a difference between the jth Gray code count summation in the N−1 Gray code count summations of the i+1th Gray code summation set and the jth Gray code count summation in the N−1 Gray code count summations of the ith Gray code summation set based on the second predetermined order, and obtaining the difference as the jth Gray code count summation difference of the N−1 Gray code count summation differences in the ith Gray code count summation difference set of the X−1 Gray code count summation difference sets, wherein the ith Gray code count summation difference set corresponds to the ith read voltage set and the i+1th read voltage set, and the jth Gray code count summation difference in the ith Gray code count summation difference set corresponds to the jth read voltage in the ith read voltage set and the jth read voltage in the i+1th read voltage set.

### Claim 6 (depends on 1)

The decoding method as claimed in claim 1, wherein determining the N−1 optimized read voltages corresponding to the second predetermined order from the X*(N−1) read voltages belonging to the X read voltage sets based on the N−1 Gray code count summation differences of each of the X−1 Gray code count summation difference sets to form the optimized read voltage set corresponding to the target word line comprises:
choosing the jth Gray code count summation difference from each of the X−1 Gray code count summation difference sets based on the second predetermined order to obtain X−1 jth Gray code count summation differences; and
deciding a jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set based on the X−1 jth Gray code count summation differences.

### Claim 7 (depends on 6)

The decoding method as claimed in claim 6, wherein deciding the jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set based on the X−1 jth Gray code count summation differences comprises:
identifying a plurality of target jth Gray code count summation differences lower than an optimized threshold from the X−1 jth Gray code count summation differences;
performing a check operation to the target jth Gray code count summation differences to identify one or more incorrect jth Gray code count summation differences from the target jth Gray code count summation differences and choosing one of remaining one or more correct jth Gray code count summation differences of the target jth Gray code count summation differences as an optimized jth Gray code count summation difference;
obtaining the Gray code count summation difference set that the optimized jth Gray code count summation difference belongs to as a Yth Gray code count summation difference set of the X−1 Gray code count summation difference sets; and
obtaining the jth read voltage in a Yth read voltage set or the jth read voltage in a Y+1th read voltage set as the jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set, wherein Y is a positive integer less than or equal to X−1 and is greater than or equal to 1.

### Claim 8 (depends on 7)

The decoding method as claimed in claim 7, wherein performing the check operation to the target jth Gray code count summation differences to identify the one or more incorrect jth Gray code count summation differences from the target jth Gray code count summation differences comprises:
identifying the Gray code count summation difference set to which one of the target jth Gray code count summation differences belongs, and identifying the respective jth Gray code counts of two Gray code summation sets corresponding to the Gray code count summation difference set to which the target jth Gray code count summation difference belongs;
determining whether one of the two jth Gray code counts exceeds a correct range;
determining that the target jth Gray code count summation difference is an incorrect target jth Gray code count summation difference if one of the two jth Gray code counts exceeds the correct range; and
determining that the target jth Gray code count summation difference is a correct target jth Gray code count summation difference if neither of the two jth Gray code counts exceeds the correct range.

### Claim 9 (depends on 8)

The decoding method as claimed in claim 8, wherein the number of the target memory cells that are read is set in advance, and the correct range is set based on a size of a storage space for storing data of the target memory cells,
wherein if the size of the storage space of the target memory cells is greater, the correct range is set to be greater, and if the size of the storage space of the target memory cells is smaller, the correct range is set to be smaller, and
wherein the correct range is further adjusted based on a maximum number of data bits that each memory cell is able to store.

### Claim 10 (depends on 1)

The decoding method as claimed in claim 1, wherein choosing the target word line of the word lines comprises:
choosing the target word line at a specific time point, wherein the specific time point meets one of the following:
when the storage device is idling for over a predetermined threshold of time;
when the storage device is turned on; and
when the number of error bits of data read from a word line exceeds an error bit threshold, wherein the word line is set to be the target word line.

### Claim 11 (depends on 1)

The decoding method as claimed in claim 1, further comprising:
identifying a plurality of statistical values of the target word line in response to choosing the target word line; and
adjusting a size of the predetermined voltage difference and a value of the second predetermined positive integer based on at least one of the statistical values,
wherein the statistical values comprise:
a value of program erase cycles of the target word line;
a read counter value of the target word line;
a retention time value of the target word line; and
the number of error bits of data stored in the target word line.

### Claim 12 (depends on 1)

The decoding method as claimed in claim 1, wherein values of j include 1 to N−1 based on the second predetermined order, and respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets comprises:
choosing an ith read voltage set of the X read voltage sets, wherein values of i include 1 to X based on the first predetermined order;
respectively reading the target memory cells by using N−1 read voltages of the ith read voltage set to obtain the read bit values corresponding to the ith read voltage set and classified into the Gray codes;
summing up the numbers of the read bit values classified into the respective Gray codes as the N Gray code counts corresponding to the ith read voltage set based on the obtained read bit values corresponding to the ith read voltage set and the Gray codes which the read bit values belong to, wherein the Gray code counts are arranged based on a third predetermined order; and
calculating N−1 Gray code count summations based on the N Gray code counts corresponding to the ith read voltage set and a fourth predetermined order, and obtaining the N−1 Gray code count summations as an ith Gray code summation set corresponding to the ith read voltage set in the X Gray code summation sets, wherein a value of a jth Gray code count summation in the N−1 Gray code count summations is a summation of last N−j Gray code counts and the fourth predetermined order is reverse of the second predetermined order.

### Claim 13 (depends on 11)

The decoding method as claimed in claim 11, wherein respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets further comprises:
calculating the N−1 Gray code count summations in each of the X Gray code summation sets based on a formula as follows:
SRi,j=Σk=j+1NCi,k,∀i∈[1,X],∀j∈[1,N−1]
wherein SRi,j represents the jth Gray code count summation in the ith Gray code summation set corresponding to the ith read voltage set, Ci,k represents a kth Gray code count in the N Gray code counts corresponding to the ith read voltage set, wherein values of k include N to 2 based on the fourth predetermined order.

### Claim 14

A storage controller, controlling a storage device comprising a rewritable non-volatile memory module, the storage controller comprising:
a connection interface circuit, coupled to a host system;
a memory interface control circuit, coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of word lines, each of the word lines comprises a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different Gray codes, a total number of the Gray codes is N, and N is a first predetermined positive integer greater than 2;
a read voltage management circuit unit; and
a processor, coupled to the connection interface circuit, the memory interface control circuit, and the read voltage management circuit unit,
wherein the processor chooses a target word line of the word lines, instructs the read voltage management circuit unit to perform a read voltage optimization operation corresponding to the target word line, a plurality of target memory cells of the target word line are programmed, and wherein in the read voltage optimization operation:
the read voltage management circuit unit respectively reads the target memory cells by using different X read voltage sets to obtain corresponding X Gray code summation sets, wherein X is a second predetermined positive integer, the X read voltage sets and the corresponding X Gray code summation sets are arranged based on a first predetermined order, a voltage difference between every pair of adjacent read voltage sets in the X read voltage sets is a predetermined voltage difference, each of the X read voltage sets has N−1 read voltages arranged based on a second predetermined order, wherein each of the X Gray code summation sets has N−1 Gray code count summations arranged based on the second predetermined order, and a jth Gray code count summation in the N−1 Gray code count summations corresponds to a jth read voltage in the N−1 read voltages, wherein the jth Gray code count summation is calculated by summing up first j Gray code counts among N Gray code counts, wherein the N Gray code counts are calculated by summing up the numbers of a plurality of read bit values classified into the respective Gray codes, wherein the read bit values are obtained by using a corresponding read voltage set to read the target memory cells,
wherein the read voltage management circuit unit further chooses every pair of adjacent Gray code summation sets in the X gray code summation sets based on the first predetermined order and calculates a Gray code count summation difference of the Gray code count summations at the same sequence position in the respective N−1 Gray code count summations between every chosen pair of two Gray code summation sets based on the second predetermined order to obtain X−1 Gray code count summation difference sets corresponding to all the chosen pairs of the Gray code summation sets, wherein each of the X−1 Gray code count summation difference sets comprises N−1 Gray code count summation differences arranged based on the second predetermined order, and a jth Gray code count summation difference in the N−1 Gray code count summation differences corresponds to the jth read voltage in the N−1 read voltages, and
wherein the read voltage management circuit unit further determines N−1 optimized read voltages corresponding to the second predetermined order from X*(N−1) read voltages belonging to the X read voltage sets based on the N−1 Gray code count summation differences of each of the X−1 Gray code count summation difference sets to form an optimized read voltage set corresponding to the target word line and complete the read voltage optimization operation corresponding to the target word line.

### Claim 15 (depends on 14)

The storage controller as claimed in claim 14, wherein:
the read voltage management circuit unit further performs a quick read voltage screening operation after the operation of choosing the target word line of the word lines to determine the X read voltage sets, wherein the quick read voltage screening operation comprises:
reading the target memory cells by using Z read voltage sets to obtain Z Gray code count sets respectively corresponding to the Z read voltage sets, wherein a voltage difference between every pair of adjacent read voltage sets of the Z read voltage sets is a second predetermined voltage difference, a value of Z is less than the second predetermined positive integer, and the second predetermined voltage difference is greater than the first predetermined voltage difference;
obtaining one of the Z read voltage sets as an initial reference read voltage set based on at least one of a first Gray code count and a last Gray code count of each of the Z Gray code count sets and a Gray code count predetermined value; and
determining the X read voltage sets based on the initial reference read voltage sets, a first Gray code count deviation, the second predetermined positive integer, and the first predetermined voltage difference.

### Claim 16 (depends on 14)

The storage controller as claimed in claim 14, wherein values of j include 1 to N−1 based on the second predetermined order, and in the operation of respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets:
the read voltage management circuit unit chooses an ith read voltage set of the X read voltage sets, wherein values of i include 1 to X based on the first predetermined order,
wherein the read voltage management circuit unit respectively reads the target memory cells by using N−1 read voltages of the ith read voltage set to obtain a plurality of read bit values corresponding to the ith read voltage set and classified into the Gray codes,
wherein the read voltage management circuit sums up the numbers of the read bit values classified into the respective Gray codes as the N Gray code counts corresponding to the ith read voltage set based on the obtained read bit values corresponding to the ith read voltage set and the Gray codes which the read bit values belong to, wherein the Gray code counts are arranged based on a third predetermined order, and
wherein the read voltage management circuit unit calculates N−1 Gray code count summations based on the N Gray code counts corresponding to the ith read voltage set and the second predetermined order, and obtains the N−1 Gray code count summations as an ith Gray code summation set corresponding to the ith read voltage set in the X Gray code summation sets, wherein a value of a jth Gray code count summation in the N−1 Gray code count summations is a summation of the first j Gray code counts.

### Claim 17 (depends on 16)

The storage controller as claimed in claim 16, wherein in the operation of respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets,
the read voltage management circuit calculates the N−1 Gray code count summations in each of the X Gray code summation sets based on a formula as follows:
SLi,j=Σk=1jCi,k,∀i∈[1,X],∀j∈[1,N−1]
wherein SLi,j represents the jth Gray code count summation in the ith Gray code summation set corresponding to the ith read voltage set, Ci,k represents a kth Gray code count in the N Gray code counts corresponding to the ith read voltage set, wherein values of k include 1 to N−1 based on the second predetermined order.

### Claim 18 (depends on 14)

The storage controller as claimed in claim 14, wherein in the operation of choosing the every pair of adjacent Gray code summation sets in the X gray code summation sets based on the first predetermined order and calculating the Gray code count summation difference of the Gray code count summations at the same sequence position in the respective N−1 Gray code count summations between every pair of adjacent Gray code summation sets based on the second predetermined order to obtain the X−1 Gray code count summation difference sets corresponding to all the chosen pairs of the Gray code summation sets,
the read voltage management circuit unit chooses an ith Gray code summation set and an i+1th Gray code summation set from the X Gray code summation sets,
wherein the read voltage management circuit unit calculates a difference between the jth Gray code count summation in the N−1 Gray code count summations of the i+1th Gray code summation set and the jth Gray code count summation in the N−1 Gray code count summations of the ith Gray code summation set based on the second predetermined order, and obtains the difference as the jth Gray code count summation difference of the N−1 Gray code count summation differences in the ith Gray code count summation difference set of the X−1 Gray code count summation difference sets, wherein the ith Gray code count summation difference set corresponds to the ith read voltage set and the i+1th read voltage set, and the jth Gray code count summation difference in the ith Gray code count summation difference set corresponds to the jth read voltage in the ith read voltage set and the jth read voltage in the i+1th read voltage set.

### Claim 19 (depends on 14)

The storage controller as claimed in claim 14, wherein in the operation of determining the N−1 optimized read voltages corresponding to the second predetermined order from the X*(N−1) read voltages belonging to the X read voltage sets based on the N−1 Gray code count summation differences of each of the X−1 Gray code count summation difference sets to form the optimized read voltage set corresponding to the target word line,
the read voltage management circuit unit chooses the jth Gray code count summation difference from each of the X−1 Gray code count summation difference sets based on the second predetermined order to obtain X−1 jth Gray code count summation differences, and
wherein the read voltage management circuit unit decides a jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set based on the X−1 jth Gray code count summation differences.

### Claim 20 (depends on 19)

The storage controller as claimed in claim 19, wherein in the operation of deciding the jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set based on the X−1 jth Gray code count summation differences,
the read voltage management circuit unit identifies a plurality of target jth Gray code count summation differences lower than an optimized threshold from the X−1 jth Gray code count summation differences,
wherein the read voltage management circuit unit performs a check operation to the target jth Gray code count summation differences to identify one or more incorrect jth Gray code count summation differences from the target jth Gray code count summation differences and chooses one of remaining one or more correct jth Gray code count summation differences of the target jth Gray code count differences as an optimized jth Gray code count summation difference,
wherein the read voltage management circuit unit obtains the Gray code count summation difference set that the optimized jth Gray code count summation difference belongs to as a Yth Gray code count summation difference set of the X−1 Gray code count summation difference sets, and
wherein the read voltage management circuit unit obtains the jth read voltage in a Yth read voltage set or the jth read voltage in a Y+1th read voltage set as the jth optimized read voltage in the N−1 optimized read voltages of the optimized read voltage set, wherein Y is a positive integer less than or equal to X−1 and is greater than or equal to 1.

### Claim 21 (depends on 20)

The storage controller as claimed in claim 20, wherein in the operation of performing the check operation to the target jth Gray code count summation differences to identify the one or more incorrect jth Gray code count summation differences from the target jth Gray code count summation differences,
the read voltage management circuit identifies the Gray code count summation difference set to which one of the target jth Gray code count summation differences belongs, and identifies the respective jth Gray code counts of two Gray code summation sets corresponding to the Gray code count summation difference set to which the target jth Gray code count summation difference belongs,
wherein the read voltage management circuit unit determines whether one of the two jth Gray code counts exceeds a correct range,
wherein the read voltage management circuit unit determines that the target jth Gray code count summation difference is an incorrect target jth Gray code count summation difference if one of the two jth Gray code counts exceeds the correct range, and
wherein the read voltage management circuit unit determines that the target jth Gray code count summation difference is a correct target jth Gray code count summation difference if neither of the two jth Gray code counts exceeds the correct range.

### Claim 22 (depends on 21)

The storage controller as claimed in claim 21, wherein the number of the target memory cells that are read is set in advance, and the correct range is set based on a size of a storage space for storing data of the target memory cells that are read,
wherein if the size of the storage space of the target memory cells is greater, the correct range is set to be greater, and if the size of the storage space of the target memory cells is smaller, the correct range is set to be smaller, and
wherein the correct range is further adjusted based on a maximum number of data bits that each memory cell is able to store.

### Claim 23 (depends on 14)

The storage controller as claimed in claim 14, wherein in the operation of choosing the target word line of the word lines,
the processor chooses the target word line at a specific time point, wherein the specific time point meets one of the following:
when the storage device is idling for over a predetermined threshold of time; and
when the number of error bits of data read from a word line exceeds an error bit threshold, wherein the word line is set to be the target word line.

### Claim 24 (depends on 14)

The storage controller as claimed in claim 14, wherein in the read voltage optimization operation,
the read voltage management circuit unit further identifies a plurality of statistical values of a target physical unit that the target word line belongs to in response to choosing the target word line,
wherein the read voltage management circuit unit further adjusts a size of the predetermined voltage difference and a value of the second predetermined positive integer based on at least one of the statistical values of the target physical unit,
wherein the statistical values comprise:
a value of program erase cycles of the target physical unit;
a read counter value of the target physical unit;
a retention time value of the target physical unit; and
the number of error bits of data stored in the target word line.

### Claim 25 (depends on 14)

The storage controller as claimed in claim 14, wherein values of j include 1 to N−1 based on the second predetermined order, and in the operation of respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets:
the read voltage management circuit unit chooses an ith read voltage set of the X read voltage sets, wherein values of i include 1 to X based on the first predetermined order,
wherein the read voltage management circuit unit respectively reads the target memory cells by using N−1 read voltages of the ith read voltage set to obtain the read bit values corresponding to the ith read voltage set and classified into the Gray codes,
wherein the read voltage management circuit sums up the numbers of the read bit values classified into the respective Gray codes as the N Gray code counts corresponding to the ith read voltage set based on the obtained read bit values corresponding to the ith read voltage set and the Gray codes which the read bit values belong to, wherein the Gray code counts are arranged based on a third predetermined order, and
wherein the read voltage management circuit unit calculates N−1 Gray code count summations based on the N Gray code counts corresponding to the ith read voltage set and a fourth predetermined order, and obtains the N−1 Gray code count summations as an ith Gray code summation set corresponding to the ith read voltage set in the X Gray code summation sets, wherein a value of a jth Gray code count summation in the N−1 Gray code count summations is a summation of last N−j Gray code counts and the fourth predetermined order is reverse of the second predetermined order.

### Claim 26 (depends on 25)

The storage controller as claimed in claim 25, wherein in the operation of respectively reading the target memory cells by using the different X read voltage sets to obtain the corresponding X Gray code summation sets,
the read voltage management circuit calculates the N−1 Gray code count summations in each of the X Gray code summation sets based on a formula as follows:
SRi,j=Σk=j+1NCi,k,∀i∈[1,X],∀j∈[1,N−1]
wherein SRi,j represents the jth Gray code count summation in the ith Gray code summation set corresponding to the ith read voltage set, Ci,k represents a kth Gray code count in the N Gray code counts corresponding to the ith read voltage set, wherein values of k include N to 2 based on the fourth predetermined order.