# US 10,482,977 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,977 B2 - Document ID: US10482977B2 - Status: Granted - Kind: B2 - Application number: 15/912,282 - Filed: 2018-03-05 - Published: 2019-03-14 - Granted: 2019-11-19 - Earliest claimed: 2017-09-14 - Assignees: Toshiba Memeory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Kei Shiraishi; Masaru Koyanagi; Mikihiko Ito; Yasuhiro Hirashima - Web page: https://patentgrep.com/patent/US10482977B2 ## CPC - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/109: {Control signal input circuits} - G11C 16/30: Power supply circuits - H02H 9/041: {using a short-circuiting device} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node. ## Claims ### Claim 1 A semiconductor memory device, comprising: a first pad to which a first voltage is supplied; a second pad to which a second voltage different from the first voltage is supplied; and a power supply protection circuit including: a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node, a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node, a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor, a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first transistor has a polarity different from polarities of the second transistor and the third transistor. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the fourth transistor has a polarity different from a polarity of the fifth transistor. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the fourth transistor has a threshold voltage lower than a threshold voltage of the first transistor. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the power supply protection circuit further includes a first resistor electrically connected in series with the third transistor between the second pad and the first node. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the power supply protection circuit further includes a second resistor electrically connected in series with the first transistor between the first pad and the first node. ### Claim 7 A semiconductor memory device, comprising: a memory cell array; an interface circuit through which commands to read from and write to the memory cell array are to be received; a power supply protection circuit connected to the interface circuit to supply voltages to the interface circuit; a first pad through which a first voltage is supplied to the power supply protection circuit; and a second pad through which a second voltage different from the first voltage is supplied to the power supply protection circuit, wherein the power supply protection circuit includes: a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node, a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node, a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor, a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the first transistor has a polarity different from polarities of the second transistor and the third transistor. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the fourth transistor has a polarity different from a polarity of the fifth transistor. ### Claim 10 (depends on 7) The semiconductor memory device according to claim 7, wherein the fourth transistor has a threshold voltage lower than a threshold voltage of the first transistor. ### Claim 11 (depends on 7) The semiconductor memory device according to claim 7, wherein the power supply protection circuit further includes a first resistor electrically connected in series with the third transistor between the second pad and the first node. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein the power supply protection circuit further includes a second resistor electrically connected in series with the first transistor between the first pad and the first node. ### Claim 13 A method of protecting a semiconductor memory device against a voltage surge at a first pad by turning on a power supply protection transistor connected between the first pad and a second pad, the power supply protection transistor being turned off when there is no voltage surge at the first pad, said method comprising: in response to a voltage at the first pad exceeding a threshold voltage, pulling up a gate voltage of the power supply protection transistor to turn on the power supply protection transistor and cause a current to flow from the first pad to the second pad; and in response to the voltage at the first pad not exceeding the threshold voltage, pulling down the gate voltage of the power supply protection transistor to turn off the power supply protection transistor and stop any current from flowing from the first pad to the second pad, wherein the gate voltage of the power supply protection transistor is equal to a voltage at a first node of the semiconductor memory device, and the semiconductor memory device includes: a first transistor including a first end electrically connected to the first pad and a second end electrically connected to the first node, a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node, a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor, a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node. ### Claim 14 (depends on 13) The method according to claim 13, wherein the first transistor has a polarity different from polarities of the second transistor and the third transistor. ### Claim 15 (depends on 14) The method according to claim 14, wherein the fourth transistor has a polarity different from a polarity of the fifth transistor. ### Claim 16 (depends on 13) The method according to claim 13, wherein the fourth transistor has a threshold voltage lower than a threshold voltage of the first transistor. ### Claim 17 (depends on 13) The method according to claim 13, wherein the power supply protection circuit further includes a first resistor electrically connected in series with the third transistor between the second pad and the first node. ### Claim 18 (depends on 17) The method according to claim 17, wherein the power supply protection circuit further includes a second resistor electrically connected in series with the first transistor between the first pad and the first node. ### Claim 19 (depends on 13) The method according to claim 13, further comprising: detecting whether or not the voltage at the first pad exceeds the threshold voltage.