# US 10,482,975 B2 · Flash memory cell with dual erase modes for increased cell endurance

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- Number: US 10,482,975 B2
- Document ID: US10482975B2
- Status: Granted
- Kind: B2
- Application number: 16/008,234
- Filed: 2018-06-14
- Published: 2019-09-19
- Granted: 2019-11-19
- Earliest claimed: 2018-03-16
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Incorporated
- Inventors: Luc Reboulet; James Walls
- Web page: https://patentgrep.com/patent/US10482975B2

## CPC

- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/0458: {comprising two or more independent floating gates which store independent data}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- H10B 41/30: characterised by the memory core region
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

## Claims

### Claim 1

A method, comprising:
providing a memory cell including a floating gate and a pair of program/erase nodes over the floating gate; and
selectively alternate between the pair of program/erase nodes after every N erase functions, wherein N is greater than 1, to perform a series of erase functions in the memory cell.

### Claim 2 (depends on 1)

The method of claim 1, wherein N is at least 10, at least 100, at least 1,000, at least 10,000, or at least 1,000,000.

### Claim 3 (depends on 1)

The method of claim 1, wherein the memory cell comprises a flash memory cell.

### Claim 4 (depends on 1)

The method of claim 1, wherein the pair of program/erase nodes comprise an erase gate and a word line.

### Claim 5 (depends on 1)

The method of claim 1, wherein the pair of program/erase nodes comprise a coupling gate and a word line.

### Claim 6

An electronic device, comprising:
a memory cell including a floating gate and a pair of program/erase nodes over the floating gate; and
erase control electronics configured to:
measure an erase current of the memory cell; and
selectively switch between the pair of program/erase nodes based at least on the measured erase current to perform a series of erase functions in the memory cell.

### Claim 7 (depends on 6)

The electronic device of claim 6, wherein the pair of program/erase nodes comprise an erase gate and a word line.

### Claim 8 (depends on 6)

The electronic device of claim 6, wherein the pair of program/erase nodes comprise a coupling gate and a word line.

### Claim 9 (depends on 6)

The electronic device of claim 6, wherein the memory cell comprises a flash memory cell.