# US 10,482,973 B2 · Memory devices including a word line defect detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,973 B2 - Document ID: US10482973B2 - Status: Granted - Kind: B2 - Application number: 16/014,222 - Filed: 2018-06-21 - Published: 2019-05-16 - Granted: 2019-11-19 - Earliest claimed: 2017-11-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co. Ltd. - Inventors: Jae-Yun Lee; Joon Soo Kwon; Byung Soo Kim; Sang-Soo Park; Il Han Park; Jong-Hoon Lee - Web page: https://patentgrep.com/patent/US10482973B2 ## CPC - G11C 16/12: Programming voltage switching circuits - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - H03K 5/135: by the use of time reference signals, e.g. clock signals - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line. ## Claims ### Claim 1 A memory device comprising: a memory cell array comprising a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the P/F determining circuit determines whether the word line is defective by comparing a first number of pulses included in the first pumping clock signal and a second number of pulses included in the compensated first reference clock signal. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the P/F determining circuit comprises a counter that is configured to count the first number of pulses included in the first pumping clock signal, and a compare logic that is configured to determine whether the word line is defective by comparing the first number of pulses included in the first pumping clock signal and the second number of pulses included in the compensated first reference clock signal. ### Claim 4 (depends on 1) The memory device of claim 1, further comprising: a determination signal generator configured to receive the pumping voltage signal and provide a determination signal by comparing the pumping voltage signal with a reference pumping voltage, wherein the clock generator is configured to generate the first pumping clock signal using the determination signal. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the compensation circuit provides the compensated first reference clock signal using the first pumping clock signal. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the compensation circuit sets the first pumping clock signal as the compensated first reference clock signal responsive to a determination that the word line is not defective. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the compensation circuit sets a first number of pulses included in the first pumping clock signal as a second number of pulses included in the compensated first reference clock signal, and wherein the P/F determining circuit determines whether the word line is defective by comparing a third number of pulses included in a second pumping clock signal that is different from the first pumping clock signal and the second number of pulses included in the compensated first reference clock signal. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the compensation circuit provides the compensated first reference clock signal using the power supply voltage. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the compensation circuit comprises a first storage unit that is configured to store a second reference clock signal and a second storage unit that is configured to store a third reference clock signal, different from the second reference clock signal, and wherein the compensation circuit sets one of the second or third reference clock signals as the compensated first reference clock signal in accordance with a level of the power supply voltage. ### Claim 10 (depends on 9) The memory device of claim 9, wherein the second reference clock signal comprises n pulses (where n is a natural number), wherein the third reference clock signal comprises m pulses (where m is a natural number different from n), wherein the compensation circuit outputs one of n or m as a first number of pulses included in the compensated first reference clock signal in accordance with the level of the power supply voltage, and wherein the P/F determining circuit determines whether the word line is defective by comparing a second number of pulses included in the first pumping clock signal and the first number of pulses included in the compensated first reference clock signal. ### Claim 11 A memory device comprising: a memory cell array comprising a memory cell and a word line that is connected to the memory cell; a voltage generator configured to receive a power supply voltage, generate a pumping clock signal, and provide an operating voltage to the word line to program the memory cell; a compensation circuit configured to provide a compensated reference clock signal that compensates for variations in the power supply voltage and; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing a first number of pulses included in the pumping clock signal and a second number of pulses included in the compensated reference clock signal. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the voltage generator comprises: a charge pump configured to provide a pumping voltage signal using the power supply voltage and the pumping clock signal; and a determination signal generator configured to receive the pumping voltage signal and provide a determination signal by comparing the pumping voltage signal with a reference pumping voltage, wherein the voltage generator is configured to generate the pumping clock signal using the determination signal. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the compensation circuit is configured to set the pumping clock signal as the compensated reference clock signal responsive to a determination that the word line is not defective. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the compensation circuit is configured to set the pumping clock signal as the compensated reference clock signal responsive to a determination that the memory cell is located in an upper part of the memory cell array. ### Claim 15 (depends on 11) The memory device of claim 11, wherein the compensation circuit is configured to provide the compensated reference clock signal based on the power supply voltage. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the compensation circuit comprises: an analog-to-digital converter configured to select one of a plurality of output terminals based on a level of the power supply voltage, wherein the compensation circuit is configured to output one of a first reference clock signal or a second reference clock signal as the compensated reference clock signal based on an output of the analog-to-digital converter. ### Claim 17 (depends on 11) The memory device of claim 11, wherein the compensation circuit provides the second number of pulses included in the compensated reference clock signal based on a level of the power supply voltage. ### Claim 18 A memory device comprising: a voltage generator configured to receive a power supply voltage, to generate an operating voltage using the power supply voltage, and to generate a pumping clock signal; a compensation circuit configured to provide a compensated reference clock signal that compensates for variations in the power supply voltage; a pass/fail (P/F) determining circuit configured to perform a comparison of a first number of pulses of the pumping clock signal and a second number of pulses of the compensated reference clock signal and to generate a pass/fail signal responsive to the comparison; and a controller configured to control operation of the memory device responsive to the pass/fail signal. ### Claim 19 (depends on 18) The memory device of claim 18, wherein the compensation circuit comprises a first storage unit that is configured to store a first reference clock signal and a second storage unit that is configured to store a second reference clock signal, different from the first reference clock signal, and wherein the compensation circuit sets one of the first or second reference clock signals as the compensated reference clock signal in accordance with a level of the power supply voltage. ### Claim 20 (depends on 18) The memory device of claim 18, wherein the compensation circuit comprises: an analog-to-digital converter configured to select one of a plurality of output terminals based on a level of the power supply voltage, wherein the compensation circuit is configured to output the compensated reference clock signal based on an output of the analog-to-digital converter.