# US 10,482,971 B2 · Semiconductor memory apparatus and operating method of the semiconductor memory apparatus

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- Number: US 10,482,971 B2
- Document ID: US10482971B2
- Status: Granted
- Kind: B2
- Application number: 16/014,306
- Filed: 2018-06-21
- Published: 2019-04-18
- Granted: 2019-11-19
- Earliest claimed: 2017-10-17
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jin Su Park; Taek Seung Kim
- Web page: https://patentgrep.com/patent/US10482971B2

## CPC

- G11C 16/10: Programming or data input circuits
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0038: {Power supply circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 2013/0076: {Write operation performed depending on read result}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.

## Claims

### Claim 1

A semiconductor memory apparatus comprising:
a memory cell; and
a current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, perform a reset write operation without limiting a voltage level across the memory cell, and limit the voltage level across the memory cell to a level of a clamping voltage in a set write operation.

### Claim 2 (depends on 1)

The semiconductor memory apparatus according to claim 1,
wherein the memory cell is coupled between a global bit line and a global word line, and
wherein the current supply circuit comprises:
a first limit circuit coupled with the global bit line, and configured to change a current applied to the memory cell; and
a second limit circuit coupled with the global word line, and configured to change a current flowing through the memory cell.

### Claim 3 (depends on 2)

The semiconductor memory apparatus according to claim 2, wherein the first limit circuit changes a voltage level of the global bit line, and the second limit circuit changes a voltage level of the global word line.

### Claim 4 (depends on 2)

The semiconductor memory apparatus according to claim 2, further comprising:
a write controller configured to control the first and second limit circuits based on a reset write signal and a set write signal.

### Claim 5 (depends on 2)

The semiconductor memory apparatus according to claim 2, further comprising:
a bit line supply configured to provide a high voltage to the first limit circuit; and
a word line supply configured to provide a low voltage having a level lower than the high voltage, to the second limit circuit.

### Claim 6 (depends on 2)

The semiconductor memory apparatus according to claim 2, further comprising:
a column switch configured to couple one end of the memory cell and the global bit line based on a bit line select signal; and
a row switch configured to couple the other end of the memory cell and the global word line based on a word line select signal.

### Claim 7

A semiconductor memory apparatus comprising:
a memory cell; and
a current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, and selectively limit a voltage level across the memory cell to a level of a clamping voltage based on whether the write operation is a set write operation or a reset write operation.

### Claim 8 (depends on 7)

The semiconductor memory apparatus according to claim 7, wherein the current supply circuit limits the voltage level across the memory cell to the level of the clamping voltage during the set write operation, and performs the reset write operation without limiting the voltage level across the memory cell to the level of the clamping voltage.

### Claim 9 (depends on 8)

The semiconductor memory apparatus according to claim 8,
wherein the memory cell is coupled between a global bit line and a global word line, and
wherein the current supply circuit comprises:
a first limit circuit coupled with the global bit line, and configured to change a current applied to the memory cell; and
a second limit circuit coupled with the global word line, and configured to change a current flowing through the memory cell.

### Claim 10 (depends on 9)

The semiconductor memory apparatus according to claim 9, wherein the first limit circuit changes a voltage level of the global bit line, and the second limit circuit changes a voltage level of the global word line.

### Claim 11 (depends on 9)

The semiconductor memory apparatus according to claim 9, further comprising:
a write controller configured to control the first and second limit circuits based on a reset write signal and a set write signal.

### Claim 12 (depends on 9)

The semiconductor memory apparatus according to claim 9, further comprising:
a bit line supply configured to provide a high voltage to the first limit circuit; and
a word line supply configured to provide a low voltage having a level lower than the high voltage, to the second limit circuit.

### Claim 13 (depends on 9)

The semiconductor memory apparatus according to claim 9, further comprising:
a column switch configured to couple one end of the memory cell and the global bit line based on a bit line select signal; and
a row switch configured to couple the other end of the memory cell and the global word line based on a word line select signal.

### Claim 14

A method for operating a semiconductor memory apparatus, comprising:
determining a resistance state of a memory cell by performing a pre-read operation when a set write operation or a reset write operation is started; and
selectively limiting a voltage across a memory cell to a level of a clamping voltage based on whether it is a set write operation or a reset write operation.

### Claim 15 (depends on 14)

The method according to claim 14, wherein a write operation is ended when the resistance state of the memory cell determined through the determining during the set write operation is a set state.

### Claim 16 (depends on 14)

The method according to claim 14, wherein a write operation is ended when the resistance state of the memory cell determined through the determining during the reset write operation is a reset state.

### Claim 17 (depends on 14)

The method according to claim 14, wherein the selectively limiting limits a level of the voltage across the memory cell to the level of the clamping voltage and provides a set pulse to the memory cell, during the set write operation.

### Claim 18 (depends on 14)

The method according to claim 14, wherein the selectively limiting does not limit a level of the voltage across the memory cell to the level of the clamping voltage and provides a reset pulse to the memory cell, during the reset write operation.

### Claim 19

A semiconductor memory apparatus comprising:
a memory cell; and
a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell prior to changing the resistance state of the memory cell.

### Claim 20 (depends on 19)

The semiconductor memory apparatus according to claim 19, wherein the current supply circuit changes the resistance state of the memory cell without limiting the voltage level across the memory cell if the state of the memory cell is a set state prior to changing the resistance state of the memory cell.

### Claim 21 (depends on 20)

The semiconductor memory apparatus according to claim 20, wherein the current supply circuit changes the resistance state of the memory cell without limiting the voltage level across the memory cell in a reset write operation.

### Claim 22 (depends on 19)

The semiconductor memory apparatus according to claim 19, wherein the current supply circuit limits the voltage level across the memory cell to the level of the clamping voltage if the state of the memory cell is a reset state prior to changing the resistance state of the memory cell.

### Claim 23 (depends on 22)

The semiconductor memory apparatus according to claim 22, wherein the current supply circuit limits the voltage level across the memory cell to the level of the clamping voltage in a set write operation.

### Claim 24 (depends on 19)

The semiconductor memory apparatus according to claim 19, wherein the amount of the current flowing through the memory cell is changed during a write operation.

### Claim 25 (depends on 19)

The semiconductor memory apparatus according to claim 19, wherein the state of the memory cell, prior to changing the resistance state of the memory cell, is determined during a pre-read operation.

### Claim 26 (depends on 19)

The semiconductor memory apparatus according to claim 19,
wherein the memory cell is coupled to a global bit line, and
wherein the current supply circuit includes a first limit circuit coupled with the global bit line, and configured to change a current applied to the memory cell by clamping the global bit line to limit the voltage level across the memory cell.

### Claim 27 (depends on 14)

The method according to claim 14, wherein the selectively limiting a voltage across the memory cell to the level of the clamping voltage is further based on the determined resistance state of the memory cell.