# US 10,482,968 B1 · Local x-decoder and related memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,968 B1 - Document ID: US10482968B1 - Status: Granted - Kind: B1 - Application number: 16/198,859 - Filed: 2018-11-22 - Granted: 2019-11-19 - Earliest claimed: 2018-11-22 - Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Inventors: Yuan Tang; Jen-Tai Hsu - Web page: https://patentgrep.com/patent/US10482968B1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 8/10: Decoders - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/30: Power supply circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system. ## Claims ### Claim 1 A local X-decoder for a memory system, comprising: a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system. ### Claim 2 (depends on 1) The local X-decoder of claim 1, wherein the decoding unit comprises: a first p-type P0 transistor comprising a source and a base coupled to a local word line signal PWL, a gate coupled to a locally global word line signal GWLb, and a drain, and configured to generate the word line signal to the memory cell; a first N-type transistor N1 comprising a drain coupled to the drain of the first p-type transistor, a gate coupled to the locally global word line signal, a base coupled to a bank mode voltage source VEEX, and a source coupled a sector voltage source SVEEX; and a second N-type transistor N2 comprising a drain coupled to the local word line signal, a gate coupled to a global word line signal GWL, a base coupled to the bank mode voltage source, and a source coupled to the drain of the first p-type transistor. ### Claim 3 (depends on 2) The local X-decoder of claim 2, wherein deep n-wells of the first N-type transistor and the second N-type transistor are coupled together, and the bases of the first N-type transistor and the second N-type transistor are formed in a triple p-well. ### Claim 4 (depends on 2) The local X-decoder of claim 2, wherein: the unselected erase mode signal is configured to indicate an unselected word line in erase mode; the bank mode voltage source is configured to select an operating mode for one of the plurality banks of the memory array of the memory system; and the sector voltage source is configured to select one of a plurality of sectors of one of the plurality banks of the memory array. ### Claim 5 (depends on 2) The local X-decoder of claim 2, wherein the unselected erase detecting unit comprises: a second P-type transistor P2 comprising a source and a base coupled to a local mode voltage source SVPPX_b, a gate coupled to the unselected erase mode signal, and a drain coupled to the gate of the first p-type transistor; a third N-type transistor N0 comprising a drain coupled to the drain of the second P-type transistor, a base coupled to the bank mode voltage source, agate coupled to the unselected erase mode signal, and a source coupled to the locally global word line signal and the gate of the first N-type transistor; and a third P-type transistor P1 comprising a source coupled to the drains of the second P-type transistor P2 and the third N-type transistor and the gate of the transistor first p-type, a gate and a base coupled to the local mode voltage source, and a drain coupled to the locally global word line signal, the source of the third N-type transistor and the gate of the first N-type transistor. ### Claim 6 (depends on 5) The local X-decoder of claim 5, wherein the bases of the second P-type transistor and the third P-type transistor are formed in an n-well, the base of the third N-type transistor is formed in a triple p-well together with the bases of the first N-type transistor and the second N-type transistor, and deep n-well of the third N-type transistor is coupled together with the first N-type transistor and the second N-type transistor. ### Claim 7 (depends on 5) The local X-decoder of claim 5, wherein third N-type transistor and the third P-type transistor are configured to separate the gates of the first N-type transistor and the first p-type transistor. ### Claim 8 (depends on 5) The local X-decoder of claim 5, wherein the local mode voltage source is configured to indicate an erase mode for the memory cell, and the memory cell is a NOR flash memory cell. ### Claim 9 (depends on 2) The local X-decoder of claim 2, wherein further comprising: a fourth N-type transistor N10 comprising a drain coupled to the source of the second N-type transistor, a gate coupled to the local mode voltage source, a base coupled to the bank mode voltage source, and a source coupled to the drains of the first p-type transistor and the first N-type transistor. ### Claim 10 (depends on 9) The local X-decoder of claim 9, wherein the fourth N-type transistor is configured to be a voltage clamping transistor in the local X-decoder to reduce a voltage difference across a gate oxide of the second N-type transistor by an amount of a threshold voltage of the fourth N-type transistor, and the base of the fourth N-type transistor is formed in a triple p-well together with the bases of the third N-type transistor, the first N-type transistor and the second N-type transistor. ### Claim 11 A memory system, comprising: a memory array comprising a memory cell; a power source configured to generate a first voltage source VPPX; a bank decoder configured to generate a local mode voltage source SVPPX_b; an erase mode decoder coupled to the bank decoder and the power source, and configured to generate an unselected erase mode signal according to the first voltage source and the local mode voltage source; a local X-decoder coupled to the memory cell and the erase mode decoder, comprising: a decoding unit configured to generate a word line signal to of the memory cell; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to the unselected erase mode signal; wherein the word line signal is floating when the memory cell is unselected in an erase mode of the memory system. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the decoding unit comprises: a first p-type transistor P0 comprising a source and a base coupled to a local word line signal PWL, a gate coupled to a locally global word line signal GWLb, and a drain, and configured to generate the word line signal to the memory cell; a first N-type transistor N1 comprising a drain coupled to the drain of the first p-type transistor, a gate coupled to the locally global word line signal, a base coupled to a bank mode voltage source VEEX, and a source coupled a sector voltage source SVEEX; and a second N-type transistor N2 comprising a drain coupled to the local word line signal, a gate coupled to a global word line signal GWL, a base coupled to the bank mode voltage source, and a source coupled to the drain of the first p-type transistor. ### Claim 13 (depends on 12) The memory system of claim 12, wherein deep n-wells of the first N-type transistor and the second N-type transistor are coupled together, and the bases of the first N-type transistor and the second N-type transistor are formed in a triple p-well. ### Claim 14 (depends on 12) The memory system of claim 12, wherein the unselected erase mode signal is configured to indicate an unselected word line in erase mode; the bank mode voltage source is configured to select an operating mode for one of the plurality banks of the memory array of the memory system; and the sector voltage source is configured to select one of a plurality of sectors of one of the plurality banks of the memory array. ### Claim 15 (depends on 12) The memory system of claim 12, wherein the unselected erase detecting unit comprises: a second P-type transistor P2 comprising a source and a base coupled to a local mode voltage source SVPPX_b, a gate coupled to the unselected erase mode signal, and a drain coupled to the gate of the first p-type transistor; a third N-type transistor N0 comprising a drain coupled to the drain of the second P-type transistor, a base coupled to the bank mode voltage source, agate coupled to the unselected erase mode signal, and a source coupled to the locally global word line signal and the gate of the first N-type transistor; and a third P-type transistor P1 comprising a source coupled to the drains of the second P-type transistor P2 and the third N-type transistor and the gate of the transistor first p-type, a gate and a base coupled to the local mode voltage source, and a drain coupled to the locally global word line signal, the source of the third N-type transistor and the gate of the first N-type transistor. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the bases of the second P-type transistor and the third P-type transistor are formed in an n-well, the base of the third N-type transistor is formed in a triple p-well together with the bases of the first N-type transistor and the second N-type transistor, and deep n-well of the third N-type transistor is coupled together with the first N-type transistor and the second N-type transistor. ### Claim 17 (depends on 15) The memory system of claim 15, wherein third N-type transistor and the third P-type transistor are configured to separate the gates of the first N-type transistor and the first p-type transistor, the local mode voltage source is configured to indicate an erase mode for the memory cell, and the memory cell is a NOR flash memory cell. ### Claim 18 (depends on 12) The memory system of claim 12, wherein the local X-decoder further comprises: a fourth N-type transistor N10 comprising a drain coupled to the source of the second N-type transistor, a gate coupled to the local mode voltage source, a base coupled to the bank mode voltage source, and a source coupled to the drains of the first p-type transistor and the first N-type transistor. ### Claim 19 (depends on 18) The memory system of claim 18, wherein the fourth N-type transistor is configured to be a voltage clamping transistor in the local X-decoder to reduce a voltage difference across a gate oxide of the second N-type transistor by an amount of a threshold voltage of the fourth N-type transistor, and the base of the fourth N-type transistor is formed in a triple p-well together with the bases of the third N-type transistor, the first N-type transistor and the second N-type transistor. ### Claim 20 (depends on 12) The memory system of claim 12, further comprising: a local word line decoder coupled to the bank decoder and the local X-decoder, and configured to generate the local word line signal PWL according to a second voltage source SVPPX; a global word line decoder coupled to the bank decoder and the local X-decoder, and configured to generate the locally global word line signal GWLb and the global word line signal GWL according to the second voltage source SVPPX and the bank mode voltage source VEEX; a sector decoder coupled to the local X-decoder, and configured to generate the sector voltage source SVEEX according to the bank mode voltage source VEEX; and a bank mode decoder coupled to the global word line decoder and the sector decoder, and configured to generate the bank mode voltage source VEEX.