# US 10,482,967 B1 · Layout structure of local x-decoder

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- Number: US 10,482,967 B1
- Document ID: US10482967B1
- Status: Granted
- Kind: B1
- Application number: 16/198,854
- Filed: 2018-11-22
- Granted: 2019-11-19
- Earliest claimed: 2018-11-22
- Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
- Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
- Inventors: Yuan Tang; Jen-Tai Hsu
- Web page: https://patentgrep.com/patent/US10482967B1

## CPC

- G11C 8/10: Decoders
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A two-sided memory array is disclosed. Each side includes four local x-decoders. Each local x-decoder includes: a first pair of cascode transistors coupled to a first signal; a second pair of cascode transistors coupled to the first signal, a second signal, and a word line; a third transistor coupled to the first signal; and a third pair of cascode transistors coupled to the second signal, a third signal, and the word line. All transistors in each local x-decoder are disposed vertically, and P-channels and N-channels on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

## Claims

### Claim 1

A two-sided memory array comprising a central Flash memory cell array, wherein each side of the memory array comprises:
four local x-decoders, each local x-decoder comprising:
a first pair of cascode transistors coupled between a voltage supply and ground, comprising a first PMOS and a first NMOS, wherein a first voltage is coupled to a gate of the first PMOS and a gate of the first NMOS, and a first signal is coupled to a drain of the first PMOS and a source of the first NMOS;
a second pair of cascode transistors comprising a second PMOS and a second NMOS, wherein a drain of the second NMOS is coupled to ground, a source of the second PMOS is coupled to a second signal, a drain of the second PMOS is coupled to a word line, and the first signal is coupled to a gate of the second PMOS;
a third PMOS, having a source coupled to the first signal and a drain coupled to ground; and
a third pair of cascode transistors comprising a third NMOS and a fourth NMOS, wherein a source of the third NMOS is coupled to the second signal, a gate of the third NMOS is coupled to a third signal, and a drain of the fourth NMOS is coupled to the word line;
wherein all transistors in each local x-decoder are disposed vertically, and P-channels and N-channels of the four local x-decoders on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

### Claim 2 (depends on 1)

The two-sided memory array of claim 1, wherein odd-numbered word lines of the local x-decoders couple the local x-decoders on a first side of the memory array to the central Flash memory and even-numbered word lines of the local x-decoders couple the local x-decoders on a second side of the memory array to the central Flash memory.