# US 10,482,966 B2 · Block decoder of nonvolatile memory and level shifter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,966 B2 - Document ID: US10482966B2 - Status: Granted - Kind: B2 - Application number: 16/153,048 - Filed: 2018-10-05 - Published: 2019-05-16 - Granted: 2019-11-19 - Earliest claimed: 2017-11-16 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Ju-An Chiang; Ya-Wen Chang - Web page: https://patentgrep.com/patent/US10482966B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - H03K 3/356113: {using additional transistors in the input circuit} - G11C 8/10: Decoders - H03K 19/018521: {of complementary type, e.g. CMOS} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A block decoder of nonvolatile memory includes a level shifter and a decoder. A first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage. A second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node. A third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to second supply voltage. A fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node. ## Claims ### Claim 1 A block decoder of nonvolatile memory, comprising: a level shifter, comprising: a first transistor, wherein the first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage; a second transistor, wherein the second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node; a third transistor, wherein the third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to a second supply voltage; and a fourth transistor, wherein the fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node; and a decoder, coupled to a third supply voltage, wherein the decoder outputs a first control voltage to the first control node and outputs a second control voltage to the second control node. ### Claim 2 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the first control voltage and the second control voltage have complementary logic levels. ### Claim 3 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein each of the first transistor, the second transistor, and the third transistor is an NMOS transistor (N-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 4 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the fourth transistor is a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 5 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein each of the first transistor, the second transistor, and the fourth transistor is an enhancement-type transistor. ### Claim 6 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the third transistor is a depletion-type transistor. ### Claim 7 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the third supply voltage is greater than or equal to an absolute value of a threshold voltage of the third transistor. ### Claim 8 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the third supply voltage is higher than the first supply voltage. ### Claim 9 (depends on 8) The block decoder of the nonvolatile memory as claimed in claim 8, wherein a voltage difference between the third supply voltage and the first supply voltage is greater than or equal to a threshold voltage of the first transistor. ### Claim 10 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the second supply voltage is at least four times the first supply voltage or the third supply voltage. ### Claim 11 (depends on 1) The block decoder of the nonvolatile memory as claimed in claim 1, wherein the decoder comprises: a fifth transistor, wherein the fifth transistor has a control terminal coupled to a first input node, a first terminal coupled to the third supply voltage, and a second terminal coupled to the second control node; a sixth transistor, wherein the sixth transistor has a control terminal coupled to the first input node, a first terminal coupled to a second node, and a second terminal coupled to the second control node; a seventh transistor, wherein the seventh transistor has a control terminal coupled to a second input node, a first terminal coupled to a third node, and a second terminal coupled to the second node; and an eighth transistor, wherein the eighth transistor has a control terminal coupled to a third input node, a first terminal coupled to the ground voltage, and a second terminal coupled to the third node. ### Claim 12 (depends on 11) The block decoder of the nonvolatile memory as claimed in claim 11, wherein the decoder further comprises: a ninth transistor, wherein the ninth transistor has a control terminal coupled to the second input node, a first terminal coupled to the third supply voltage, and a second terminal coupled to the second control node; a tenth transistor, wherein the tenth transistor has a control terminal coupled to the third input node, a first terminal coupled to the third supply voltage, and a second terminal coupled to the second control node; and an inverter, coupled to the third supply voltage, wherein the inverter has an input terminal coupled to the second control node, and an output terminal coupled to the first control node. ### Claim 13 (depends on 12) The block decoder of the nonvolatile memory as claimed in claim 12, wherein each of the fifth transistor, the ninth transistor, and the tenth transistor is a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 14 (depends on 12) The block decoder of the nonvolatile memory as claimed in claim 12, wherein each of the sixth transistor, the seventh transistor, and the eighth transistor is an NMOS transistor (N-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 15 A level shifter, comprising: a first transistor, wherein the first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage; a second transistor, wherein the second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node; a third transistor, wherein the third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to a second supply voltage; and a fourth transistor, wherein the fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node. ### Claim 16 (depends on 15) The level shifter as claimed in claim 15, wherein a first control voltage at the first control node and a second control voltage at the second control node have complementary logic levels. ### Claim 17 (depends on 15) The level shifter as claimed in claim 15, wherein each of the first transistor, the second transistor, and the third transistor is an NMOS transistor (N-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 18 (depends on 15) The level shifter as claimed in claim 15, wherein the fourth transistor is a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor). ### Claim 19 (depends on 15) The level shifter as claimed in claim 15, wherein each of the first transistor, the second transistor, and the fourth transistor is an enhancement-type transistor. ### Claim 20 (depends on 15) The level shifter as claimed in claim 15, wherein the third transistor is a depletion-type transistor.