# US 10,482,963 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,963 B2 - Document ID: US10482963B2 - Status: Granted - Kind: B2 - Application number: 15/703,078 - Filed: 2017-09-13 - Published: 2018-03-15 - Granted: 2019-11-19 - Earliest claimed: 2016-09-14 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Daisuke Hagishima - Web page: https://patentgrep.com/patent/US10482963B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to one embodiment, a semiconductor memory device includes a stacked body including a first stacked region, and a first structure body. The first stacked region includes first and second selection gate electrodes, first electrodes arranged in a first direction and provided between the first and second selection gate electrodes, second electrodes arranged in the first direction and provided between the second selection gate electrode and the first electrodes, and third electrodes arranged in the first direction and provided between the first electrodes and the second electrodes. A first spacing between two mutually-adjacent first electrodes is wider than a third spacing between two mutually-adjacent third electrodes. A second spacing between two mutually-adjacent second electrodes is wider than the third spacing. ## Claims ### Claim 1 A semiconductor memory device, comprising: a stacked body including a first stacked region; and a first structure body, the first stacked region including a first selection gate electrode, a second selection gate electrode separated from the first selection gate electrode in a first direction, a plurality of first electrodes arranged in the first direction and provided between the first selection gate electrode and the second selection gate electrode, a plurality of second electrodes arranged in the first direction and provided between the second selection gate electrode and the first electrodes, and a plurality of third electrodes arranged in the first direction and provided between the first electrodes and the second electrodes, a first spacing between two mutually-adjacent first electrodes of the first electrodes being wider than a third spacing between two mutually-adjacent third electrodes of the third electrodes, a second spacing between two mutually-adjacent second electrodes of the second electrodes being wider than the third spacing, the first structure body including a first semiconductor body extending in the first direction, a first outer film provided between the first semiconductor body and the first stacked region, a first inner film provided between the first semiconductor body and the first outer film, and a first intermediate film provided between the first outer film and the first inner film. ### Claim 2 (depends on 1) The device according to claim 1, further comprising: a second structure body; a first conductive layer; and a second conductive layer, the stacked body further including a third selection gate electrode, a direction connecting the second selection gate electrode and the third selection gate electrode and being aligned with a second direction, the second direction crossing the first direction, the first selection gate electrode including a first selection gate region separated from the third selection gate electrode in the first direction, the first electrodes including a first electrode region between the first selection gate region and the third selection gate electrode, the second electrodes including a second electrode region between the first selection gate region and the first electrode region, the third electrodes including a third electrode region between the first electrode region and the second electrode region, the stacked body including a second stacked region, the second stacked region including the first selection gate region, the third selection gate electrode, the first electrode region, the second electrode region, and the third electrode region, the second structure body including a second semiconductor body extending in the first direction, a second outer film provided between the second semiconductor body and the second stacked region, a second inner film provided between the second semiconductor body and the second outer film, and a second intermediate film provided between the second outer film and the second inner film, the first semiconductor body including a first end portion and a second end portion, the second semiconductor body including a third end portion and a fourth end portion, the first conductive layer being electrically connected to the first end portion and the third end portion, the second conductive layer being electrically connected to the second end portion and the fourth end portion. ### Claim 3 (depends on 2) The device according to claim 2, further comprising a controller electrically connected to the first conductive layer, the second conductive layer, the first selection gate electrode, the second selection gate electrode, the first electrodes, the second electrodes, and the third electrodes, the controller being configured to perform a first operation of setting the first conductive layer to a first potential, setting the second conductive layer to a second potential, setting one of the third electrodes to a third potential higher than the first potential and higher than the second potential, setting the first electrodes to a fourth potential between the first potential and the third potential, setting the second electrodes to a fifth potential between the second potential and the third potential, setting at least one other third electrode of the third electrodes other than the one of the third electrodes to a sixth potential, the sixth potential being between the fourth potential and the third potential and between the fifth potential and the third potential, setting the second selection gate electrode to a seventh potential lower than the fourth potential and lower than the fifth potential, setting the first selection gate electrode to an eighth potential lower than the seventh potential, and setting the third selection gate electrode to a ninth potential lower than the seventh potential. ### Claim 4 (depends on 3) The device according to claim 3, wherein in the first operation, the controller is configured to perform setting, to a tenth potential, at least another one of the third electrodes positioned between the first electrodes and the at least one of the third electrodes set to the sixth potential, and setting, to an eleventh potential, at least another one of the third electrodes positioned between the second electrodes and the at least one of the third electrodes set to the sixth potential, the tenth potential being between the fourth potential and the sixth potential, the eleventh potential being between the fifth potential and the sixth potential. ### Claim 5 (depends on 4) The device according to claim 4, wherein the absolute value of a difference between the tenth potential and the sixth potential is 2 volts or less. ### Claim 6 (depends on 1) The device according to claim 1, further comprising a base body, the stacked body being provided on a surface of the base body, the first direction crossing the surface. ### Claim 7 (depends on 1) The device according to claim 1, wherein the first structure body extends in the first direction through the stacked body. ### Claim 8 (depends on 3) The device according to claim 3, wherein the absolute value of a difference between the sixth potential and the first potential is not less than 0.4 times and not more than 0.6 times the absolute value of a difference between the third potential and the first potential. ### Claim 9 (depends on 3) The device according to claim 3, wherein the absolute value of a difference between the fourth potential and the first potential is not less than 0.4 times and not more than 0.8 times a difference between the sixth potential and the first potential. ### Claim 10 (depends on 3) The device according to claim 3, wherein the controller is configured to set all of the other third electrodes of the third electrodes to the sixth potential in the first operation. ### Claim 11 (depends on 4) The device according to claim 4, wherein the absolute value of a difference between the fourth potential and the first potential is not less than 0.4 times but less than 0.7 times a difference between the sixth potential and the first potential. ### Claim 12 (depends on 4) The device according to claim 4, wherein the absolute value of a difference between the tenth potential and the first potential is not less than 0.7 times and not more than 0.9 times a difference between the sixth potential and the first potential. ### Claim 13 (depends on 1) The device according to claim 1, wherein a ratio of a first length to the total of the first length, a second length, and a third length is not less than 0.05 and not more than 0.15, the first length being a length in the first direction of a region including the first electrodes, the second length being a length in the first direction of a region including the second electrodes, the third length being a length in the first direction of a region including the third electrodes. ### Claim 14 (depends on 1) The device according to claim 1, wherein the controller is configured to further implement a second operation of setting a potential of at least one of the third electrodes to be lower than a potential of the first conductive layer and lower than a potential of the second conductive layer. ### Claim 15 (depends on 1) The device according to claim 1, wherein the controller is configured to further implement a third operation of setting the first conductive layer to a twelfth potential, setting the second conductive layer to a thirteenth potential different from the twelfth potential, and setting at least one of the third electrodes to a fourteenth potential, the absolute value of a difference between the fourteenth potential and the twelfth potential and the absolute value of a difference between the fourteenth potential and the thirteenth potential being less than the absolute value of a difference between the third potential and the first potential. ### Claim 16 (depends on 1) The device according to claim 1, wherein a difference between the first spacing and the third spacing is not less than 2 nanometers and not more than 10 nanometers, and a difference between the second spacing and the third spacing is not less than 2 nanometers and not more than 10 nanometers. ### Claim 17 (depends on 1) The device according to claim 1, wherein the first spacing is not less than 1.05 times and not more than 1.5 times the third spacing, and the second spacing is not less than 1.05 times and not more than 1.5 times the third spacing. ### Claim 18 (depends on 1) The device according to claim 1, wherein a thickness of the first semiconductor body along a direction from the first inner film toward the first outer film is not less than 10 nanometers and not more than 30 nanometers. ### Claim 19 (depends on 7) The device according to claim 7, wherein the first inner film is provided around the first semiconductor body, the first intermediate film is provided around the first inner film, and the first outer film is provided around the first intermediate film. ### Claim 20 (depends on 7) The device according to claim 7, wherein the first structure body further includes a first core portion extending in the first direction, and the first semiconductor body is provided around the first core portion.