# US 10,482,958 B2 · RRAM-based monotonic counter

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- Number: US 10,482,958 B2
- Document ID: US10482958B2
- Status: Granted
- Kind: B2
- Application number: 15/898,119
- Filed: 2018-02-15
- Published: 2019-01-31
- Granted: 2019-11-19
- Earliest claimed: 2017-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Lien Linus Lu; Yu-Der Chih; Chung-Cheng Chou; Tong-Chern Ong
- Web page: https://patentgrep.com/patent/US10482958B2

## CPC

- G11C 13/0038: {Power supply circuits}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 12/1425: {the protection being physical, e.g. cell, word, block}
- G06F 21/64: Protecting data integrity, e.g. using checksums, certificates or signatures
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0059: {Security or protection circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G06F 2212/1036: Life time enhancement
- G06F 2212/1052: Security improvement
- G06F 2212/177: Smart card
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

## Claims

### Claim 1

A circuit, comprising:
a memory array having a plurality of memory cells;
a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state;
a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state; and
an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the plurality of memory cells each comprises a resistive random access memory (RRAM) cell.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the first memory cell presents a substantially lower resistance value when the first memory cell transitions from the first resistance state to the second resistance state.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the first memory cell presents a substantially lower resistance value when the first memory cell transitions from the second resistance state to the third resistance state.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein when the first memory cell transitions to the third resistance state, the first memory cell cannot transition back to either the first or second resistance states.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the control logic circuit is further configured to use the first voltage signal to cause a second memory cell of the plurality of memory cells to transition from a respective first resistance state to a respective second resistance state.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein the counter circuit is further configured to increment the respective count by one in response to the second memory cell's transition from the respective first to the respective second resistance states.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the first voltage signal is a positive value, and the second voltage signal is a negative value.

### Claim 9

A circuit, comprising:
a memory array having a plurality of resistive random access memory (RRAM) cells;
a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first RRAM cell of the plurality of RRAM cells to transition from a first resistance state to a second resistance state; and
a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first RRAM cell's transition from the first to the second resistance state; and
an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the control logic circuit is further configured to use a second voltage signal to cause the first RRAM cell to transition from the second resistance state to a third resistance state.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the counter circuit is further configured to again increment the count by one in response to the first RRAM cell's transition from the second to the third resistance state.

### Claim 12 (depends on 10)

The circuit of claim 10, wherein when the first RRAM cell transitions to the third resistance state, the first RRAM cell cannot transition back to either the first or second resistance state.

### Claim 13 (depends on 10)

The circuit of claim 10, wherein the first RRAM cell presents a substantially lower resistance value when the first RRAM cell transitions from the second resistance state to the third resistance state.

### Claim 14 (depends on 9)

The circuit of claim 9, wherein the first RRAM cell presents a substantially lower resistance value when the RRAM memory cell transitions from the first resistance state to the second resistance state.

### Claim 15 (depends on 9)

The circuit of claim 9, wherein the control logic circuit is further configured to use the first voltage signal to cause a second RRAM cell of the plurality of RRAM cells to transition from a respective first resistance state to a respective second resistance state.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein the counter circuit is further configured to increment the respective count by a one in response to the second RRAM cell's transition from the respective first to the respective second resistance state.

### Claim 17

A method, comprising:
providing a memory cell that is in a first resistance state;
transitioning the memory cell from the first resistance state to a second resistance state;
incrementing a count of a counter by one in response to the memory cell's transition from the first to second resistance state;
transitioning the memory cell from the second resistance state to a third resistance state;
again incrementing the count of the counter by one in response to the memory cell's transition from the second to third resistance state; and
generating an encrypted value using an updated count provided by the counter.

### Claim 18 (depends on 17)

The method of claim 17, wherein when the memory cell transitions to the third resistance state, the memory cell cannot transition back to either the first or second resistance state.

### Claim 19 (depends on 17)

The method of claim 17, wherein the memory cell comprises a resistive random access memory (RRAM) cell.

### Claim 20 (depends on 17)

The method of claim 17, wherein when the memory cell transitions from the first resistance state to the second resistance state, the first memory cell presents a lower resistance value, and when the memory cell transitions from the second resistance state to the third resistance state, the memory cell presents an even lower resistance value.