# US 10,482,957 B2 · Resistive RAM memory cell

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- Number: US 10,482,957 B2
- Document ID: US10482957B2
- Status: Granted
- Kind: B2
- Application number: 15/978,003
- Filed: 2018-05-11
- Published: 2018-11-15
- Granted: 2019-11-19
- Earliest claimed: 2017-05-12
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: Stmicroelectronics (Rousset) SAS
- Inventors: Philippe Boivin; Simon Jeannot; Olivier Weber
- Web page: https://patentgrep.com/patent/US10482957B2

## CPC

- G11C 13/003: {Cell access}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0023: {Address circuits or decoders}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/821: {Device geometry}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.

## Claims

### Claim 1

A memory cell comprising:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in a substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the memory element rests at least partially on a top surface of the gate of the selection transistor.

### Claim 2 (depends on 1)

The memory cell according to claim 1, in which the memory element includes L-shaped constituent layers having substantially vertical portions that extend along the sidewall of the gate and substantially horizontal portions that extend at least partially on the conductive zone of selection transistor.

### Claim 3 (depends on 2)

The memory cell according to claim 2, in which the constituent layers of the memory element include a conductive contact spacer that extends on the L-shaped constituent layer and does not extend above a height of the gate.

### Claim 4 (depends on 1)

The memory cell according to claim 1, in which the memory element is of OxRAM type.

### Claim 5 (depends on 1)

The memory cell according to claim 1, in which the memory element and the transistor are formed on a silicon-on-insulator substrate.

### Claim 6 (depends on 1)

The memory cell according to claim 1, in which the memory element comprises, on said conductive zone, a layer of a metal oxide chosen from the group consisting of HfO2 and Ta2O5 and a layer of an oxidizable metal chosen from the group comprising consisting of titanium and hafnium.

### Claim 7 (depends on 1)

The memory cell according to claim 1, in which said conductive zone is made of titanium nitride.

### Claim 8

A memory, comprising:
a substrate layer; and
first and second memory cells each including:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side, wherein in each of the first and second memory cells, the memory element of the memory cell rests at least partially on a top surface of the gate of the selection transistor of the memory cell.

### Claim 9 (depends on 8)

The memory according to claim 8, wherein the substrate layer is part of a silicon-on-insulator substrate.

### Claim 10 (depends on 9)

The memory according to claim 9, comprising insulation between the conductive zone of the first memory cell and the conductive zone of the second memory cell.

### Claim 11 (depends on 8)

The memory according to claim 8, wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is spaced apart from, and electrically connected to, the first contact.

### Claim 12 (depends on 8)

The memory according to claim 8, wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is contiguous with the first contact.

### Claim 13 (depends on 8)

The memory according to claim 8, wherein in each of the first and second memory cells, the memory element includes L-shaped constituent layers having substantially vertical portions that extend along the sidewall of the gate and substantially horizontal portions that extend at least partially on the conductive zone of the selection transistor of the memory cell.

### Claim 14 (depends on 13)

The memory according to claim 13, wherein in each of the first and second memory cells, the constituent layers of the memory element include a conductive contact spacer that extends on the L-shaped constituent layer and does not extend above a height of the gate of the selection transistor of the memory cell.

### Claim 15 (depends on 8)

The memory according to claim 8, wherein in each of the first and second memory cells, the memory element comprises, on said conductive zone, a layer of a metal oxide chosen from the group consisting of HfO2 and Ta2O5 and a layer of an oxidizable metal chosen from the group consisting of titanium and hafnium.

### Claim 16

A memory, comprising:
a silicon on insulator substrate that includes a semiconductor layer on a buried insulating layer;
first and second memory cells each including:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side; and
an insulating region extending between the conductive zone of the first memory cell and the conductive zone of the second memory cell, the insulating region including a portion of the buried insulating layer.

### Claim 17 (depends on 16)

The memory according to claim 16, wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is spaced apart from, and electrically connected to, the first contact.

### Claim 18 (depends on 16)

The memory according to claim 16, wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is contiguous with the first contact.