# US 10,482,954 B2 · Phase change memory device

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- Number: US 10,482,954 B2
- Document ID: US10482954B2
- Status: Granted
- Kind: B2
- Application number: 15/686,308
- Filed: 2017-08-25
- Published: 2017-12-07
- Granted: 2019-11-19
- Earliest claimed: 2006-07-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fabio Pellizzer; Roberto Bez; Ferdinando Bedeschi; Roberto Gastaldi
- Web page: https://patentgrep.com/patent/US10482954B2

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

## Claims

### Claim 1

A memory system, comprising:
a memory array comprising multiple memory cells, each coupled to a data bitline, the memory cells arranged in groups with the memory cells of each group coupled to a single wordline;
multiple reference cells, each reference cell connected to a reference bitline, with at least two reference cells associated with each group of memory cells; and
a current/voltage converter connected to the data bitlines and reference bitlines through data bitline switches and reference bitline switches, each of the reference bitline switches being sequentially and alternately operated, during a read operation in a respective group, to sequentially and alternately direct a reference current from the respective reference cell to the current/voltage converter.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the current/voltage converter includes a reference load coupled to each reference bitline, the reference loads each comprising a transistor having a gate and drain shorted together.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the current/voltage converter further includes a data load coupled to each data bitline, and wherein the reference loads and data loads are connected to form a current mirror.

### Claim 4 (depends on 1)

The memory system of claim 1, further comprising comparators coupled to respective data bitlines, wherein an output of the current/voltage converter is provided to the comparators to sequentially and alternately compare voltages corresponding to each reference current to a reference voltage VREF.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein each reference cell is programmed to generate one of a number of reference currents.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the number of reference currents is based on the number of possible states of the memory cells.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein each of the reference cells and memory cells includes a phase change memory element.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein each of the reference cells and memory cells include a selection element.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein each data bitline switch is closed for the duration of the read operation to simultaneously read each memory cell of the group.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein each reference cell is formed next to the associated group of memory cells.

### Claim 11

A method of accessing a memory device, the method comprising:
for each group of memory cells coupled to a wordline of a memory array with each wordline having an associated two or more reference cells, the memory cells coupled to data bitlines and the reference cells coupled to reference bitlines, the memory device further including a current/voltage converter connected to the data bitlines and reference bitlines through data bitline switches,
sequentially and alternately operating each of the reference bitline switches during a read operation in a respective group, to sequentially and alternately direct a reference current from the respective reference cell to the current/voltage converter; and
providing the reference current to comparators associated with each memory cell of the respective group; and
comparing the reference current from the respective reference cell with a reference current associated with each memory cell of the respective group to read a state of each memory cell.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
in a programming operation, programming a memory cell to one of at least a set state and a reset state; and
programming the associated two or more reference cells proximate in time to the programming of the memory cell.

### Claim 13 (depends on 12)

The method of claim 12, wherein the two or more reference cells are programmed to generate one of a number of reference currents, and wherein the number of reference currents is based on the number of possible states of the memory cells.

### Claim 14 (depends on 12)

The method of claim 12, wherein the programming operation is performed in a time span of 1-10 microseconds, with programming of a group of memory cells being performed simultaneously.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
providing an output of the current/voltage converter to comparators coupled to respective data bitlines to sequentially and alternately compare voltages corresponding to each reference current to a reference voltage VREF.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
during the read operation, simultaneously closing each data bitline switch; and
simultaneously reading each memory cell of the group.

### Claim 17

A system comprising:
a controller; and
a memory coupled to the controller, the memory comprising a memory array comprising multiple memory cells, each coupled to a data bitline, the memory cells arranged in groups with the memory cells of each group coupled to a single wordline;
multiple reference cells, each reference cell connected to a reference bitline, with at least two reference cells associated with each group of memory cells; and
a current/voltage converter connected to the data bitlines and reference bitlines through data bitline switches and reference bitline switches, each of the reference bitline switches being sequentially and alternately operated, during a read operation in a respective group, to sequentially and alternately direct a reference current from the respective reference cell to the current/voltage converter.

### Claim 18 (depends on 17)

The system of claim 17, wherein the current/voltage converter includes a reference load coupled to each reference bitline and a data load coupled to each data bitline, the reference loads and the data loads coupled together through respective gate terminals in a current mirror configuration.

### Claim 19 (depends on 17)

The system of claim 17, wherein the memory further includes comparators coupled to respective data bitlines, wherein an output of the current/voltage converter is provided to the comparators to sequentially and alternately compare voltages corresponding to each reference current to a reference voltage VREF.

### Claim 20 (depends on 17)

The system of claim 17, wherein each of the reference cells and memory cells includes a phase change memory element having similar structure and a selection element.