# US 10,482,952 B2 · Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,952 B2 - Document ID: US10482952B2 - Status: Granted - Kind: B2 - Application number: 15/861,308 - Filed: 2018-01-03 - Published: 2018-05-10 - Granted: 2019-11-19 - Earliest claimed: 2005-07-01 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Brian J. Campbell; Vincent R. von Kaenel; Daniel C. Murray; Gregory S. Scott; Sribalan Santhanam - Web page: https://patentgrep.com/patent/US10482952B2 ## CPC - G11C 11/419: Read-write [R-W] circuits - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 11/417: for memory cells of the field-effect type - H03K 3/35613: {the input circuit having a differential configuration} - H03K 19/018528: {with at least one differential stage} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. ## Claims ### Claim 1 An integrated circuit comprising: a logic circuit in a first voltage domain, the first voltage domain corresponding to a first power supply voltage having a first power supply voltage value during use; a memory circuit in a second voltage domain corresponding to a second power supply voltage having a second power supply voltage value different from the first power supply voltage value for at least some operation during use, the memory circuit comprising a plurality of memory cells, wherein the logic circuit accesses data in the memory circuit; and an interface circuit between the first voltage domain and the second voltage domain, wherein the interface circuit converts one or more inputs to the memory circuit from the logic circuit from the first voltage domain to the second voltage domain. ### Claim 2 (depends on 1) The integrated circuit as recited in claim 1 wherein the interface circuit comprises a level shifting circuit that incorporates at least one logic function into the conversion of the one or more inputs. ### Claim 3 (depends on 2) The integrated circuit as recited in claim 2 wherein the level shifting circuit converts a first input of the one or more inputs from the first voltage domain to the second voltage domain. ### Claim 4 (depends on 3) The integrated circuit as recited in claim 3 wherein the logic function is a clock gating logic function and the first input is a precharge clock for the memory circuit. ### Claim 5 (depends on 4) The integrated circuit as recited in claim 4 wherein an output of the level shifting circuit is input to one or more word line driver circuits of the memory circuit. ### Claim 6 (depends on 1) The integrated circuit as recited in claim 1 wherein the interface circuit further converts data output from the plurality of memory cells from the second voltage domain to the first voltage domain. ### Claim 7 (depends on 6) The integrated circuit as recited in claim 6 wherein the interface circuit comprises at least one sense amplifier configured to sense data from the plurality of memory cells. ### Claim 8 (depends on 7) The integrated circuit as recited in claim 7 wherein the sense amplifier converts the data output from the plurality of memory cells to the first voltage domain. ### Claim 9 (depends on 1) The integrated circuit as recited in claim 1 further comprising a plurality of input conductors to the integrated circuit, wherein the first power supply voltage is supplied on one or more first input conductors of the plurality of input conductors. ### Claim 10 (depends on 9) The integrated circuit as recited in claim 9 wherein the second power supply voltage is supplied on one or more second input conductors of the plurality of input conductors that are separate from the first input conductors. ### Claim 11 (depends on 1) The integrated circuit as recited in claim 1 wherein the interface circuit is included in the memory circuit. ### Claim 12 An integrated circuit comprising: a logic circuit in a first voltage domain, the first voltage domain corresponding to a first power supply and a first power supply voltage having a first power supply voltage value during use; a memory array comprising a plurality of memory cells, wherein the plurality of memory cells are in a second voltage domain corresponding to a second power supply voltage having a second power supply voltage value different from the first power supply voltage value at least for at least a subset of memory operations during use, and wherein the logic reads and writes data to the memory array; and an interface between the first and second voltage domains comprising level shifting circuitry, wherein the level shifting circuitry: converts voltage levels of one or more of address, timing, control, address, and input data output from the logic circuit and input to the memory array into voltage levels supplied to the plurality of memory cells, and; converts voltage levels of data output from the plurality of memory cells into voltage levels supplied to the logic circuit. ### Claim 13 (depends on 12) The integrated circuit as recited in claim 12 further comprising a plurality of input conductors to the integrated circuit, wherein the second power supply voltage is supplied on one or more first input conductors of the plurality of input conductors, and wherein the first power supply voltage is supplied on one or more second input conductors of the plurality of input conductors that are separate from the first input conductors. ### Claim 14 (depends on 12) The integrated circuit as recited in claim 12 wherein the level shifting circuitry level shifts a clock to precharge circuitry in the memory array. ### Claim 15 (depends on 14) The integrated circuit as recited in claim 14 wherein the level shifting circuitry performs a logic function on the clock during the level shift. ### Claim 16 (depends on 15) The integrated circuit as recited in claim 15 wherein the logic function is clock gating with an input enable signal from the logic circuit. ### Claim 17 An integrated circuit comprising: first and second voltage inputs coupled to an external electrical energy source during use, the external electrical energy source providing at least a first voltage on the first voltage input during operation; and logic circuitry receiving electrical energy from the external electrical energy source during operation, a plurality of memory cells receiving electrical energy from the external electrical energy source during operation, and an interface circuit coupled to the logic circuitry and to the plurality of memory cells, wherein: the logic circuitry accesses data in the plurality of memory cells; the plurality of memory cells store data; the second voltage is different from the first voltage at least during some time intervals during operation; the interface circuitry is coupled to the first and second voltage inputs; the plurality of memory cells are operable from the second voltage; and the interface circuitry converts voltage levels of data output from the at least one of the plurality of memory cells operable from the second voltage to the voltage levels of the logic circuitry operable from the first voltage. ### Claim 18 (depends on 17) The integrated circuit as recited in claim 17 wherein the interface circuitry converts voltage levels of one or more inputs from the logic circuitry to the plurality of memory cells from the first voltage to the second voltage. ### Claim 19 (depends on 18) The integrated circuit as recited in claim 18 wherein interface circuitry comprises level shifting circuitry that also performs a logic function on the one or more inputs during the data conversion. ### Claim 20 (depends on 19) The integrated circuit as recited in claim 19 wherein the logic function is clock gating of a clock signal in the level shifting circuitry with an input enable signal. ### Claim 21 (depends on 17) The integrated circuit as recited in claim 17 wherein a memory circuit includes the plurality of memory cells and the interface circuitry.