# US 10,482,950 B2 ยท Static random access memory devices including a plurality of storage cells and a read/write circuit > Agents: this data is available as JSON from the patentgrep API and MCP server โ€” see https://patentgrep.com/llms.txt - Number: US 10,482,950 B2 - Document ID: US10482950B2 - Status: Granted - Kind: B2 - Application number: 14/390,455 - Filed: 2013-04-03 - Published: 2015-10-15 - Granted: 2019-11-19 - Earliest claimed: 2012-04-04 - Assignees: Platipus Limited - Applicants: Silicon Basis Ltd - Inventors: Robert Charles Beat - Web page: https://patentgrep.com/patent/US10482950B2 ## CPC - G11C 11/419: Read-write [R-W] circuits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/412: using field-effect transistors only - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalization. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a โ€˜1โ€™ to the plurality of storage cells. ## Claims ### Claim 1 A static random access memory device including: a plurality of storage cells arranged in a stack; and a read-write circuit that is separate from the plurality of storage cells, the read-write circuit configured to modify a state of a storage cell of the plurality of storage cells, wherein the read-write circuit comprises a plurality of access transistors, the number of access transistors of the plurality of access transistors being equal to the number of storage cells and each one of the plurality of access transistors having a dedicated connection between a data node of a respective different one of the plurality of storage cells and a common read-write data node of the read-write circuit. ### Claim 2 (depends on 1) A static random access memory according to claim 1 wherein each storage cell of the plurality of storage cells includes a cross coupled inverter circuit that provides a latch circuit. ### Claim 3 (depends on 1) A static random access memory according to claim 1 wherein each access transistor of the plurality of access transistors is controlled by a corresponding wordline control signal. ### Claim 4 (depends on 1) A static random access memory according to claim 1 wherein each of the dedicated connections that connect each storage cell of the plurality of storage cells to the read-write circuit exhibits a capacitance. ### Claim 5 (depends on 4) A static random access memory access device according to claim 4 wherein each of the dedicated connections that connect each storage cell of the plurality of storage cells to the read-write circuit exhibits a larger capacitance than the common read-write data node of the read-write circuit. ### Claim 6 (depends on 4) A static random access memory device according to claim 4 wherein the read-write circuit includes a write data connection and means for connecting the write data connection to the common read-write data node of the read-write circuit to permit data to be written to a storage cell of the plurality of storage cells. ### Claim 7 (depends on 6) A static random access memory device according to claim 6 further comprising means for lowering a supply voltage to a first storage cell of the plurality of storage cells. ### Claim 8 (depends on 7) A static random access memory device according to claim 7 wherein the plurality of storage cells are supplied by a separate power supply. ### Claim 9 (depends on 7) A static random access memory device according to claim 7 wherein the means for lowering the supply voltage to the first storage cell of the plurality of storage cells comprises a switch that reduces the voltage supplied to the storage cell. ### Claim 10 (depends on 9) A static random access memory device according to claim 9 wherein the switch comprises an NMOS source-follower header, a PMOS source-follower footer, a PMOS threshold voltage drop header or an NMOS threshold voltage drop footer. ### Claim 11 (depends on 7) A static random access memory device according to claim 7 further comprising a regulator internal to the static random access memory device, the regulator being configured to generate a supply voltage to the storage cell of the plurality of storage cells from a supply voltage to the static random access memory device. ### Claim 12 (depends on 6) A static random access memory device according to claim 6 wherein each storage cell of the plurality of storage cells includes a cross coupled inverter circuit which provides a latch circuit and wherein the cross coupled inverter circuit of each storage cell comprises an NMOS having a source terminal, the static random access memory device further comprising a switch that isolates the source terminal of the NMOS of the cross coupled inverter circuit from ground. ### Claim 13 (depends on 1) A static random access memory device according to claim 1 further comprising a voltage recovery circuit associated with the common read-write data node for increasing a voltage at the common read-write data node during a read operation of the static random access memory device. ### Claim 14 (depends on 1) A static random access memory device according to claim 1 further comprising means for pre-charging the read-write data node to a supply voltage of the static random access memory device, to increase a voltage at the common read-write data node during a read operation of the static random access memory device. ### Claim 15 (depends on 1) A static random access memory device according to claim 1 wherein each of the plurality of access transistors comprises a full transmission gate with both NMOS and PMOS devices. ### Claim 16 (depends on 1) A static random access memory device according to claim 1 wherein the plurality of storage cells is arranged in a column format with the read write circuit. ### Claim 17 A static random access memory device including: a plurality of storage cells; and a read-write circuit that is separate from the plurality of storage cells, the read-write circuit configured to modify a state of a storage cell of the plurality of storage cells, wherein the read-write circuit comprises a plurality of access transistors, the number of access transistors of the plurality of access transistors being equal to the number of storage cells and each one of the plurality of access transistors having a dedicated connection between a data node of a respective different one of the plurality of storage cells and a common read-write data node of the read-write circuit, wherein each access transistor of the plurality of access transistors is controlled by a corresponding different wordline control signal, the static random access memory device further comprising boost or voltage pump circuitry configured operable to increase a voltage on each of the wordlines to a level above that of a supply voltage of the static random access memory device. ### Claim 18 A static random access memory device including: a plurality of storage cells arranged in a stack; and a read-write circuit that is separate from the plurality of storage cells, the read-write circuit configured to modify a state of a storage cell of the plurality of storage cells, the read-write circuit comprising: a common read-write data node; and a plurality of access transistors, the number of access transistors of the plurality of access transistors being equal to the number of storage cells and each one of the plurality of access transistors having a dedicated connection between a data node of a respective different one of the plurality of storage cells and the common read-write data node of the read-write circuit, each of the dedicated connections exhibiting a larger capacitance than the common read-write data node.