# US 10,482,949 B2 · Semiconductor device

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- Number: US 10,482,949 B2
- Document ID: US10482949B2
- Status: Granted
- Kind: B2
- Application number: 16/272,123
- Filed: 2019-02-11
- Published: 2019-06-06
- Granted: 2019-11-19
- Earliest claimed: 2014-10-31
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Yuichiro Ishii; Atsushi Miyanishi; Kazumasa Yanagisawa
- Web page: https://patentgrep.com/patent/US10482949B2

## CPC

- G11C 11/417: for memory cells of the field-effect type
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10W 20/427: {Power or ground buses}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.

## Claims

### Claim 1

A semiconductor device including a first mode and a second mode different from the first mode, comprising:
a memory circuit comprised of a first switch, a memory array, and a peripheral circuit;
a first power source line electrically coupled with an I/O circuit of the peripheral circuit, and supplied with a first voltage in the first mode; and
a second power source line electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode,
wherein the first switch is comprised of a first field effect transistor and a second field effect transistor,
wherein a source of the first field effect transistor is electrically coupled with the first power source line,
wherein a source of the second field effect transistor is electrically coupled with the second power source line,
wherein the first field effect transistor is formed on a first well located in a region where the memory cell is formed, and
wherein the second field effect transistor is formed on a second well located in a region where the I/O circuit is formed.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein, in plan view, the first field effect transistor and the second field effect transistor are located between the memory array and the I/O circuit.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein, in plan view, the first field effect transistor is located between the second field effect transistor and the I/O circuit.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein a second switch is formed outside the region where the memory circuit is formed, and
wherein the second switch includes a third field effect transistor having a source electrically coupled with the first power source line, and a fourth field effect transistor having a source electrically coupled with the second power source line.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first mode is an active mode, and
wherein the second mode is an active mode and a standby mode.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein each of the first field effect transistor and the second field effect transistor is a p-type field effect transistor.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein each of the first well and the second well is an n-type impurity region.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein a drain of the first field effect transistor and a drain of the second field effect transistor are electrically connected to each other.