# US 10,482,944 B2 · Semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,944 B2 - Document ID: US10482944B2 - Status: Granted - Kind: B2 - Application number: 15/947,467 - Filed: 2018-04-06 - Published: 2019-03-21 - Granted: 2019-11-19 - Earliest claimed: 2017-09-19 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Kihun Kwon; Jaeil Kim - Web page: https://patentgrep.com/patent/US10482944B2 ## CPC - G11C 11/40607: {Refresh operations in memory devices with an internal cache or data buffer} - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/4082: {Address Buffers; level conversion circuits} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device includes an initial buffer signal generation circuit and a buffer signal generation circuit. The initial buffer signal generation circuit includes an initial buffer circuit which is activated if an initialization operation terminates. The initial buffer signal generation circuit generates an initial buffer signal from an external control signal in response to a first reference voltage signal. The buffer signal generation circuit includes a buffer circuit which is activated in response to the initial buffer signal. The buffer signal generation circuit generates a buffer signal from the external control signal in response to a second reference voltage signal. ## Claims ### Claim 1 A semiconductor device comprising: an initial buffer signal generation circuit configured to include an initial buffer circuit which is activated if an initialization operation terminates and configured to generate an initial buffer signal from an external control signal in response to a first reference voltage signal; and a buffer signal generation circuit configured to include a buffer circuit which is activated in response to the initial buffer signal and configured to generate a buffer signal from the external control signal in response to a second reference voltage signal; wherein the initial buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal, and wherein the initial buffer signal has a second logic level if the external control signal has a level which is less than the level of the first reference voltage signal. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the external control signal is a chip selection signal which is enabled to activate a chip including the semiconductor device. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the initial buffer circuit is inactivated in response to the initial buffer signal. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first reference voltage signal has a half level of a power supply voltage which is provided by an external device; and wherein the second reference voltage signal has a same level as the power supply voltage. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the initial buffer circuit is inactivated if the initial buffer signal has the first logic level; and wherein the buffer circuit is activated if the initial buffer signal has the first logic level. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the initial buffer circuit compares the external control signal with the first reference voltage signal to generate a pre-initial buffer signal, in response to an initial buffer activation signal; and wherein the initial buffer signal generation circuit further includes: a buffer control signal generation circuit configured to generate a buffer control signal from a signal of a node which is driven in response to a reset signal and a termination activation signal; and an initial buffer signal output circuit configured to generate the initial buffer signal in response to the pre-initial buffer signal and the buffer control signal. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the initial buffer activation signal is enabled if the initialization operation terminates. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the reset signal is enabled to perform the initialization operation; wherein the termination activation signal is enabled if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal; and wherein the buffer control signal is enabled if both the reset signal and the termination activation signal are disabled. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the buffer circuit compares the external control signal with the second reference voltage signal in response to a buffer activation signal; and wherein the buffer signal generation circuit further includes a selection output circuit that buffers an output signal of the buffer circuit to selectively output the buffer signal in response to a command buffer flag. ### Claim 10 (depends on 1) The semiconductor device of claim 1, further comprising a buffer control circuit configured to receive the initial buffer signal to generate a termination activation signal for activating a termination resistor circuit connected to a command/address buffer and to generate a buffer activation signal for activating the buffer circuit. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising a command/address input control circuit configured to generate a command/address buffer activation signal for controlling activation or inactivation of a command/address buffer in response to an initial buffer activation signal, a reset signal and the buffer signal. ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising a refresh control circuit configured to generate a refresh exit signal in response to the initial buffer signal and a refresh signal. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the refresh exit signal is enabled if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal to cause a level transition of the initial buffer signal, while a refresh signal is enabled to perform a refresh operation. ### Claim 14 A semiconductor device comprising: a buffer signal generation circuit configured to include a buffer circuit which is activated in response to an initial buffer signal which is generated by comparing an external control signal with a first reference voltage signal if an initialization operation terminates and configured to generate a buffer signal from the external control signal in response to a second reference voltage signal; and a command/address input control circuit configured to generate a command/address buffer activation signal for controlling activation or inactivation of a command/address buffer in response to the buffer signal; wherein the initial buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal, and wherein the initial buffer signal has a second logic level if the external control signal has a level which is less than the level of the first reference voltage signal. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the external control signal is a chip selection signal which is enabled to activate a chip including the semiconductor device. ### Claim 16 (depends on 14) The semiconductor device of claim 14, wherein the first reference voltage signal has a half level of a power supply voltage which is provided by an external device; and wherein the second reference voltage signal has a same level as the power supply voltage. ### Claim 17 (depends on 14) The semiconductor device of claim 14, wherein the buffer circuit is activated if the initial buffer signal has the first logic level. ### Claim 18 (depends on 14) The semiconductor device of claim 14, wherein the buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the second reference voltage signal; and wherein the buffer signal has a second logic level if the external control signal has a level which is less than the level of the second reference voltage signal. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the command/address buffer activation signal is enabled if the buffer signal has the first logic level. ### Claim 20 (depends on 14) The semiconductor device of claim 14, further comprising a buffer control circuit configured to receive the initial buffer signal to generate a termination activation signal for activating a termination resistor circuit connected to the command/address buffer and to generate a buffer activation signal for activating the buffer circuit. ### Claim 21 A semiconductor device comprising: an initial buffer signal generation circuit configured to include an initial buffer circuit which is activated if an initialization operation terminates and configured to generate an initial buffer signal from an external control signal in response to a reference voltage signal; and a refresh control circuit configured to generate a refresh exit signal in response to the initial buffer signal and a refresh signal; wherein the initial buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the reference voltage signal, and wherein the initial buffer signal has a second logic level if the external control signal has a level which is less than the level of the reference voltage signal. ### Claim 22 (depends on 21) The semiconductor device of claim 21, wherein the external control signal is a chip selection signal which is enabled to activate a chip including the semiconductor device. ### Claim 23 (depends on 21) The semiconductor device of claim 21, wherein the initial buffer circuit is inactivated if the initial buffer signal has the first logic level. ### Claim 24 (depends on 21) The semiconductor device of claim 21, wherein the initial buffer circuit compares the external control signal with the reference voltage signal to generate a pre-initial buffer signal, in response to an initial buffer activation signal; and wherein the initial buffer signal generation circuit further includes: a buffer control signal generation circuit configured to generate a buffer control signal from a signal of a node which is driven in response to a reset signal and a termination activation signal; and an initial buffer signal output circuit configured to generate the initial buffer signal in response to the pre-initial buffer signal and the buffer control signal. ### Claim 25 (depends on 24) The semiconductor device of claim 24, wherein the initial buffer activation signal is enabled if the initialization operation terminates. ### Claim 26 (depends on 24) The semiconductor device of claim 24, wherein the reset signal is enabled to perform the initialization operation; wherein the termination activation signal is enabled if the external control signal has a level which is greater than or equal to a level of the reference voltage signal; and wherein the buffer control signal is enabled if both the reset signal and the termination activation signal are disabled. ### Claim 27 (depends on 21) The semiconductor device of claim 21, wherein the refresh exit signal is enabled if the external control signal has a level which is greater than or equal to a level of the reference voltage signal to cause a level transition of the initial buffer signal, while the refresh signal is enabled to perform a refresh operation.