# US 10,482,943 B2 · Systems and methods for improved error correction in a refreshable memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,482,943 B2
- Document ID: US10482943B2
- Status: Granted
- Kind: B2
- Application number: 15/636,565
- Filed: 2017-06-28
- Published: 2019-01-03
- Granted: 2019-11-19
- Earliest claimed: 2017-06-28
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Dexter Chun; Yanru Li
- Web page: https://patentgrep.com/patent/US10482943B2

## CPC

- G11C 11/40607: {Refresh operations in memory devices with an internal cache or data buffer}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 2211/4062: Parity or ECC in refresh operations
- H03M 13/098: {using single parity bit}
- H03M 13/11: using multiple parity bits
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.

## Claims

### Claim 1

A method for implementing error correction control (ECC) on a computing device, the method comprising:
defining a parity region and a user data region of a refreshable memory device, the memory device coupled to a system on a chip (SoC), the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
determining with the SoC a first refresh rate for the user data region of the memory device;
determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of: a ratio to the first refresh rate, and calibration data;
generating with the SoC parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
refreshing the user data region of the memory device at the first refresh rate;
refreshing the parity region of the memory device at the second refresh rate; and
determining that a change in the second refresh rate for the parity region is needed based on at least one of: a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

### Claim 2 (depends on 1)

The method of claim 1, wherein the refreshable memory device comprises a dynamic random access memory (DRAM).

### Claim 3 (depends on 2)

The method of claim 2, wherein the parity region of the DRAM comprises a plurality of sequential memory addresses of the DRAM and the user data region of the DRAM comprises a second plurality of sequential memory addresses of the DRAM.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
storing the generated parity data in an ECC cache of the SoC; and
writing the generated parity data stored in the ECC cache to the parity region of the memory device at a different time than the associated user data is provided to the user data region of the memory device.

### Claim 5 (depends on 4)

The method of claim 4, wherein the generated parity data comprises one or more parity words having a length corresponding to a word-length of the memory device, the one or more parity words including parity bits for multiple write operations from the SoC to the memory device.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
writing one or more of the parity words from the ECC cache to the parity region of the memory device.

### Claim 7 (depends on 1)

The method of claim 1, wherein the calibration data is generated by calibration tests performed on the memory device while the memory device is coupled to the SoC, wherein the calibration data corresponds to the number of memory errors detected at different refresh rates under varying conditions of the memory device.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
during operation of the SoC, changing the second refresh rate for the parity region of the refreshable memory to a third refresh rate, the third refresh rate different from the first refresh rate.

### Claim 9

A computer system for implementing error correction control (ECC), the system comprising:
a refreshable memory device, the memory device comprising a parity region and a user data region, the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
a system on a chip (SoC) in communication with the memory device; and
logic of the SoC configured to:
determine a first refresh rate for the user data region of the memory device;
determine a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of: a ratio to the first refresh rate, and calibration data;
generate parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
refresh the user data region of the memory device at the first refresh rate;
refresh the parity region of the memory device at the second refresh rate; and
determining that a change in the second refresh rate for the parity region is needed based on at least one of: a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

### Claim 10 (depends on 9)

The system of claim 9, wherein the refreshable memory device comprises a dynamic random access memory (DRAM).

### Claim 11 (depends on 10)

The system of claim 10, wherein the parity region of the DRAM comprises a plurality of sequential memory addresses of the DRAM and the user data region of the DRAM comprises a second plurality of sequential memory addresses of the DRAM.

### Claim 12 (depends on 9)

The system of claim 9, wherein the SoC further comprises an ECC module with an ECC cache, the ECC module configured to store the generated parity data in the ECC cache and to write the generated parity data stored in the ECC cache to the parity region of the memory device at a different time than the associated user data is provided to the user data region of the memory device.

### Claim 13 (depends on 12)

The system of claim 12, wherein the generated parity data comprises one or more parity words having a length corresponding to a word-length of the memory device, the one or more parity words including parity bits for multiple write operations from the SoC to the memory device.

### Claim 14 (depends on 13)

The system of claim 13, wherein the logic is further configured to:
write one or more of the parity words from the ECC cache to the parity region of the memory device.

### Claim 15 (depends on 9)

The system of claim 9, wherein the calibration data is generated by calibration tests performed on the memory device while the memory device is coupled to the SoC, wherein the calibration data corresponds to the number of memory errors detected at different refresh rates under varying conditions of the memory device.

### Claim 16 (depends on 9)

The system of claim 9, wherein the logic of the SoC is further configured to:
during operation of the SoC, changing the second refresh rate for the parity region of the refreshable memory to a third refresh rate, the third refresh rate different from the first refresh rate.

### Claim 17

A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for implementing error correction control (ECC) on a computing device, the method comprising:
defining a parity region and a user data region of a refreshable memory device, the memory device coupled to a system on a chip (SoC), the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
determining with the SoC a first refresh rate for the user data region of the memory device;
determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of: a ratio to the first refresh rate, and calibration data;
generating parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
refreshing the user data region of the memory device at the first refresh rate;
refreshing the parity region of the memory device at the second refresh rate; and
determining that a change in the second refresh rate for the parity region is needed based on at least one of: a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

### Claim 18 (depends on 17)

The computer program product of claim 17, wherein the refreshable memory device comprises a dynamic random access memory (DRAM).

### Claim 19 (depends on 18)

The computer program product of claim 18, wherein the parity region of the DRAM comprises a plurality of sequential memory addresses of the DRAM and the user data region of the DRAM comprises a second plurality of sequential memory addresses of the DRAM.

### Claim 20 (depends on 17)

The computer program product of claim 17, further comprising:
storing the generated parity data in an ECC cache of the SoC; and
writing the generated parity data stored in the ECC cache to the parity region of the memory device at a different time than the associated user data is provided to the user data region of the memory device.

### Claim 21 (depends on 20)

The computer program product of claim 20, wherein the generated parity data comprises one or more parity words having a length corresponding to a word-length of the memory device, the one or more parity words including parity bits for multiple write operations from the SoC to the memory device.

### Claim 22 (depends on 21)

The computer program product of claim 21, further comprising:
writing one or more of the parity words from the ECC cache to the parity region of the memory device.

### Claim 23 (depends on 17)

The computer program product of claim 17, wherein the calibration data is generated by calibration tests performed on the memory device while the memory device is coupled to the SoC, the calibration tests comprising logging a number of memory errors at different refresh rates under varying conditions of the memory device.

### Claim 24

A computer system for implementing error correction control (ECC) on a computing device, the system comprising:
means for defining a parity region and a user data region of a refreshable memory device, the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits, the memory device coupled to a system on a chip (SoC);
means for determining with the SoC a first refresh rate for the user data region of the memory device;
means for determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of: a ratio to the first refresh rate, and calibration data;
means for generating parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
means for refreshing the user data region of the memory device at the first refresh rate;
means for refreshing the parity region of the memory device at the second refresh rate; and
means for determining that a change in the second refresh rate for the parity region is needed based on at least one of: a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

### Claim 25 (depends on 24)

The system of claim 24, wherein the parity region of the DRAM comprises a plurality of sequential memory addresses of the DRAM and the user data region of the DRAM comprises a second plurality of sequential memory addresses of the DRAM.

### Claim 26 (depends on 24)

The system of claim 24, further comprising:
means for storing the generated parity data in an ECC cache of the SoC; and
means for writing the generated parity data stored in the ECC cache to the parity region of the memory device at a different time than the associated user data is provided to the user data region of the memory device.

### Claim 27 (depends on 26)

The system of claim 26, wherein the generated parity data comprises one or more parity words having a length corresponding to a word-length of the memory device, the one or more parity words including parity bits for multiple write operations from the SoC to the memory device.

### Claim 28 (depends on 27)

The system of claim 27, further comprising:
means for writing one or more of the parity words from the ECC cache to the parity region of the memory device.

### Claim 29 (depends on 28)

The system of claim 28, wherein the calibration data is generated by calibration tests performed on the memory device while the memory device is coupled to the SoC, the calibration tests comprising logging a number of memory errors at different refresh rates under varying conditions of the memory device.