# US 10,482,942 B2 · Semiconductor device and system

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- Number: US 10,482,942 B2
- Document ID: US10482942B2
- Status: Granted
- Kind: B2
- Application number: 15/947,382
- Filed: 2018-04-06
- Published: 2018-10-11
- Granted: 2019-11-19
- Earliest claimed: 2017-04-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sang Kwon Lee; Kwang Soon Kim; Young Hoon Kim; Young Jun Yoon; Kyu Dong Hwang
- Web page: https://patentgrep.com/patent/US10482942B2

## CPC

- G11C 11/34: using semiconductor devices
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1087: {Data input latches}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

## Claims

### Claim 1

A semiconductor device comprising:
a first buffer configured to buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal;
a second buffer configured to generate a second data strobe buffering signal based on the first input signal and a reference voltage;
a divider circuit configured to divide the second data strobe buffering signal to generate a divided signal and a divided bar signal; and
an internal signal generation circuit configured to generate a first data latch timing signal, a second data latch timing signal, a third data latch timing signal and a fourth data latch timing signal having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided bar signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first and second input signals have opposite phases, the first data strobe buffering signal and the first data strobe bar buffering signal have opposite phases, and the divided signal and the divided bar signal have opposite phases.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first buffer generates the first data strobe buffering signal and the first data strobe bar buffering signal based on a voltage level difference between the first input signal and the second input signal.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second buffer determines a voltage level of the first input signal by comparing a voltage level of the first input signal with a voltage level of the reference voltage and buffers the determined first input signal to generate the second data strobe buffering signal.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the internal signal generation circuit generates the first and second data latch timing signals based on the first data strobe buffering signal, the divided signal and the divided bar signal, and the internal signal generation circuit generates the third and fourth data latch timing signals based on the first data strobe bar buffering signal and the first and second data latch timing signals.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the internal signal generation circuit latches the divided signal and the divided bar signal at a specific timing of the first data strobe buffering signal to output latched signals as the first and second data latch timing signals, and the internal signal generation circuit latches the first and second data latch timing signals at a specific timing of the first data strobe bar buffering signal to output latched signals as the third and fourth data latch timing signals.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the internal signal generation circuit comprises:
a first flip-flop configured to sample the divided signal and the divided bar signal at a rising period of the first data strobe buffering signal to output sampled signals as the first and second data latch timing signals; and
a second flip-flop configured to sample the first and second data latch timing signals at a rising period of the first data strobe bar buffering signal to output sampled signals as the third and fourth data latch timing signals.

### Claim 8

A semiconductor device comprising:
a first buffer configured to generate and output a first buffering signal and a first buffering bar signal based on an input signal and an input bar signal;
a second buffer configured to generate and output a second buffering signal based on the input signal and a reference voltage;
a selection circuit configured to transmit any one of the first and second buffering signals to a divider circuit based on a selection signal; and
a synchronizing circuit configured to synchronize divide signals provided from the divider and to generate a plurality of data latch timing signals,
wherein the synchronizing circuit includes:
a first synchronizing circuit configured to synchronize the divided signals with the first buffering signal, to output a first and second data latch timing signals; and
a second synchronizing circuit configured to receive the first and second data latch timing signals and synchronize the first and second data latch timing signals with the first buffering bar signal.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first buffer generates the first buffering signal and the first buffering bar signal based on a voltage level difference between the input signal and the input bar signal.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the second buffer determines a voltage level of the input signal by comparing a voltage level of the reference voltage with the voltage level of the input signal to generate determined results as the second buffering signal.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second buffer performs buffering operations on the determined results to generate the second buffering signal.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the selection circuit outputs the first buffering signal when the selection signal has a first level, and the selection circuit outputs the second buffering signal when the selection signal has a second level.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the input signal comprises a data strobe signal.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor device generates the selection signal based on a set signal, which is generated based on a command and an address, and a fuse signal, which is generated based on a cutting of a fuse.