# US 10,482,938 B2 · Word-line timing control in a semiconductor memory device and a memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,938 B2 - Document ID: US10482938B2 - Status: Granted - Kind: B2 - Application number: 15/691,985 - Filed: 2017-08-31 - Published: 2018-05-03 - Granted: 2019-11-19 - Earliest claimed: 2016-11-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jong-Pil Son; Seong-Il O - Web page: https://patentgrep.com/patent/US10482938B2 ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device. ## Claims ### Claim 1 A method of operating a semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the method comprising: enabling a first word-line of the plurality of word-lines in response to a first command received from a memory controller, the first word-line being selected in response to an access address received from the memory controller; generating an interval signal having a first pulse width if the first command corresponds to an active command; and counting the generated interval signal to determine whether a reference time interval has elapsed, and disabling the first word-line upon determining the reference time interval has elapsed, wherein a first bit-line of a bit-line pair coupled to at least one memory cell coupled to the first word-line is charged with an internal voltage and a second bit-line of the bit-line pair is discharged to a ground voltage in an enable interval during which the first word-line is enabled, and wherein voltage levels of the first and second bit-lines are maintained at the internal voltage and the ground voltage, respectively, during a disable interval during which the first word-line is disabled. ### Claim 2 (depends on 1) The method of claim 1, wherein the first word-line is disabled upon determining the reference time interval has elapsed and upon determining that a second command is not received from the memory controller during the reference time interval. ### Claim 3 (depends on 2) The method of claim 2, wherein the counting of the generated interval signal is performed by timer logic counting toggling of a clock signal received from the memory controller during a comparison time interval, and wherein a sub word-line driver is configured to disable the first word-line by applying a negative voltage having a level lower than a ground voltage to the first word-line, and wherein the sub word-line driver is connected to the first word-line. ### Claim 4 (depends on 1) The method of claim 1, further comprising disabling the first word-line in response to a disable command, wherein the memory controller is configured to apply the disable command to the semiconductor memory device when a write command to be applied to the semiconductor memory device is not present in a command queue in the memory controller during a predetermined time interval after the active command is applied to the first word-line. ### Claim 5 (depends on 1) The method of claim 1, further comprising: receiving a second command from the memory controller during the disable interval during which the first word-line is disabled; and performing a memory operation directed by the second command on the memory cell array. ### Claim 6 (depends on 5) The method of claim 5, wherein when the second command comprises a write command to direct a write operation on the memory cell array, the method further comprises: enabling the first word-line with a boosted voltage level; and writing data received from the memory controller to memory cells coupled to the first word-line in response to the write command, wherein the first bit-line is pre-charged with the internal voltage and the second bit-line is maintained at a boosted sense voltage greater than the ground voltage during the disable interval, and wherein the first bit-line is maintained at the internal voltage and the second bit-line is discharged to the ground voltage during an enable interval during which the first word-line is enabled with the boosted voltage level. ### Claim 7 (depends on 5) The method of claim 5, wherein when the second command comprises the read command to direct a read operation on the memory cell array, the method further comprises: reading data from memory cells coupled to the first word-line in response to the read command. ### Claim 8 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines; a control logic circuit configured to control access to the memory cell array; and a timing control circuit configured to: generate first control signals to control voltage levels of the word-lines in response to operation control signals provided from the control logic circuit; enable a first word-line of the plurality of word-lines in response to a first command received from a memory controller, the first word-line being selected in response to an access address received from the memory controller; generate an interval signal having a first pulse width if the first command corresponds to an active command; count the generated interval signal to determine whether a reference time interval has elapsed, and disable the first word-line upon determining the reference time interval has elapsed, wherein a first bit-line of a bit-line pair coupled to at least one memory cell coupled to the first word-line is charged with an internal voltage and a second bit-line of the bit-line pair is discharged to a ground voltage in an enable interval during which the first word-line is enabled, and wherein voltage levels of the first and second bit-lines are maintained at the internal voltage and the ground voltage, respectively, during a disable interval during which the first word-line is disabled. ### Claim 9 (depends on 8) The semiconductor memory device of claim 8, wherein the timing control circuit disables the first word-line by application of a negative voltage having a value lower than the ground voltage to the first word-line. ### Claim 10 (depends on 8) The semiconductor memory device of claim 8, wherein the first word-line is disabled upon a determination that the reference time interval has elapsed and upon a determination that a second command is not received from the memory controller during the reference time interval. ### Claim 11 (depends on 10) The semiconductor memory device of claim 10, wherein the count of the interval signal is based on a count of toggling of a clock signal received from the memory controller during the reference time interval. ### Claim 12 (depends on 8) The semiconductor memory device of claim 8, wherein the timing control circuit is further configured to generate second control signals to control voltage levels of a bit-line pair coupled to at least one memory cell coupled to the first word-line, and wherein the timing control circuit comprises: a timer logic configured to receive the operation control signals, configured to compare a duration time interval after a first operation control signal is applied with the reference time interval and configured to generate a decision signal which is activated at a time point at which the duration time interval becomes substantially the same as the reference time interval, wherein the first operation control signal corresponds to the first command; and a word-line control signal generator configured to generate first and second word-line control signals to control a voltage level of the first word-line, in response to a decoded address which is decoded from the access address and the decision signal. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, further comprising a sub word-line driver connected to the first word-line, wherein the sub word-line driver is configured to provide a negative voltage to the first word-line to disable the first word-line in response to a transition of the second word-line control signal, and wherein the word-line control signal generator is configured to transit the second word-line control signal in response to a transition of the decision signal. ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, wherein when a second command comprises a write command to direct a write operation on the memory cell array and the second command is received from the memory controller during the disable interval during which the first word-line is disabled, the control logic circuit is configured to control the timing control logic to enable the first word-line with a boosted voltage level and the control logic circuit is configured to write data received from the memory controller to memory cells coupled to the first word-line. ### Claim 15 (depends on 14) The semiconductor memory device of claim 14, wherein the timing control circuit is configured to: charge the first bit-line of a bit-line pair with the internal voltage and maintain a voltage of the second bit-line at a boosted sense voltage greater than the ground voltage during a disable interval during which the first word-line is disabled, wherein the bit-line pair is coupled to at least one memory cell coupled to the first word-line; and maintain a voltage of the first bit-line at the internal voltage and discharge the second bit-line with the ground voltage during an enable interval when the first word-line is enabled with the boosted voltage level. ### Claim 16 (depends on 12) The semiconductor memory device of claim 12, wherein when a second command comprises a read command to direct a read operation on the memory cell array during the disable interval during which the first word-line is disabled, the control logic circuit is configured to control the timing control circuit to maintain the first word-line at a negative voltage and the control logic circuit is configured to read data from memory cells coupled to the first word-line, and wherein the memory cell array comprises a three-dimensional memory cell array. ### Claim 17 A method of operating a semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the method comprising: enabling a first word-line of the plurality of word-lines in response to a first command received from a memory controller, the first word-line being selected in response to an access address received from the memory controller; and disabling the first word-line after a reference time interval elapses, wherein the reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, wherein the reference time interval corresponds to a time interval equal to or greater than a row active time (tRAS) interval of the semiconductor memory device, wherein a first bit-line of a bit-line pair coupled to at least one memory cell coupled to the first word-line is charged with an internal voltage and a second bit-line of the bit-line pair is discharged to a ground voltage in an enable interval during which the first word-line is enabled, and wherein voltage levels of the first and second bit-lines are maintained at the internal voltage and the ground voltage, respectively, during a disable interval during which the first word-line is disabled. ### Claim 18 (depends on 17) The method of claim 17, the first word-line is disabled by application of a negative voltage having a value lower than a ground voltage to the first word-line.