# US 10,482,932 B2 · Voltage reference computations for memory decision feedback equalizers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,932 B2 - Document ID: US10482932B2 - Status: Granted - Kind: B2 - Application number: 16/204,716 - Filed: 2018-11-29 - Published: 2019-03-28 - Granted: 2019-11-19 - Earliest claimed: 2017-09-26 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Jennifer E. Taylor; Raghukiran Sreeramaneni - Web page: https://patentgrep.com/patent/US10482932B2 ## CPC - G11C 7/02: with means for avoiding parasitic signals - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1066: {Output synchronization} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/1093: {Input synchronization} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)} - H04L 25/03885: {adaptive} - G11C 2207/107: Serial-parallel conversion of data or prefetch - G11C: STATIC STORES (semiconductor memory devices H10B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output. ## Claims ### Claim 1 A device, comprising: a voltage reference generator configured to produce one or more distortion correction factors; and a selection circuit configured to: receive the one or more distortion correction factors from the voltage reference generator; select a distortion correction factor of the one or more distortion correction factors as a selected distortion correction factor; and transmit the selected distortion correction factor such that the selected distortion correction factor is used to offset an interference associated with a data stream on a distorted bit. ### Claim 2 (depends on 1) The device of claim 1, comprising a latching element having a first input configured to be coupled to the selection circuit, wherein the first input is configured to receive the selected distortion correction factor. ### Claim 3 (depends on 2) The device of claim 2, wherein the latching element is configured to generate a control signal as a binary representation of one or more previous bits of the data stream, and wherein the selection circuit is configured to receive the control signal and select the distortion correction factor based upon the control signal. ### Claim 4 (depends on 2) The device of claim 2, wherein the latching element comprises a second input configured to receive the distorted bit, wherein the latching element is configured to generate a modified value of the distorted bit based upon the distortion correction factor and the distorted bit. ### Claim 5 (depends on 4) The device of claim 4, comprising a deserializer coupled to the latching element, wherein the deserializer is configured to receive the modified value of the distorted bit from the latching element and to store an indication of the modified value of the distorted bit. ### Claim 6 (depends on 5) The device of claim 5, wherein the deserializer is configured to store the indication of the modified value of the distorted bit as a binary representation of one or more previous bits of the data stream. ### Claim 7 (depends on 2) The device of claim 2, comprising a deserializer coupled to the latching element, wherein the deserializer is configured to generate a control signal as a binary representation of one or more previous bits of the data stream, wherein the selection circuit is configured to receive the control signal and select the distortion correction factor based upon the control signal. ### Claim 8 (depends on 1) The device of claim 1, wherein the selection circuit comprises a switch configured to selectively transmit the selected distortion correction factor when the switch is activated via a control signal generated based at least in part on one or more previous bits of the data stream. ### Claim 9 (depends on 1) The device of claim 1, wherein the selection circuit comprises a multiplexer. ### Claim 10 (depends on 1) The device of claim 1, wherein the distortion correction factors are equal in number to a total number of possible binary states of one or more previous bits of the data stream. ### Claim 11 (depends on 10) The device of claim 10, wherein the total number of possible binary states of a control signal is dependent upon a number of stored values of the one or more previous bits of the data stream, and wherein the control signal is utilized by the selection circuit to select the selected distortion correction factor. ### Claim 12 A device, comprising: a latching element having: a first input configured to receive a selected distortion correction factor; and a second input configured to receive a distorted bit, wherein the distorted bit has been distorted based at least in part on an interference associated with one or more previously transmitted bits of a data stream; a first output configured to transmit a control signal based at least in part on the one or more previously transmitted bits, wherein the control signal is utilized to select the selected distortion correction factor; and a second output configured to transmit a corrected bit by combining the selected distortion correction factor with the distorted bit. ### Claim 13 (depends on 12) The device of claim 12, wherein the control signal comprises a binary representation of the one or more previously transmitted bits of the data stream. ### Claim 14 (depends on 12) The device of claim 12, comprising a selection circuit coupled to the first input and the first output, wherein the selection circuit is configured to: receive the control signal; and select the selected distortion correction factor based upon the control signal. ### Claim 15 (depends on 12) The device of claim 12, comprising a deserializer coupled to the latching element, wherein the deserializer is configured to store an indication of the corrected bit. ### Claim 16 (depends on 15) The device of claim 15, wherein the deserializer is configured to store the indication of the correct bit as part of a binary representation the one or more previously transmitted bits of the data stream. ### Claim 17 A method, comprising: transmitting a selected distortion correction factor to a latching element; transmitting a distorted bit to the latching element; and generating, via the latching element, a modified value of the distorted bit based at least in part on the selected distortion correction factor and the distorted bit. ### Claim 18 (depends on 17) The method of claim 17, wherein the selected distortion correction factor is selected based at least in part on a control signal associated with one or more previously transmitted modified values of distorted bits. ### Claim 19 (depends on 18) The method of claim 18, comprising transmitting the control signal from the latching element based upon stored indications of values of a set number of the one or more previously transmitted modified values of distorted bits. ### Claim 20 (depends on 17) The method of claim 17, generating the modified value of the distorted bit as a corrected bit value having compensated for inter-symbol interference due to a predetermined number of one or more previously transmitted modified values of distorted bits.