# US 10,482,931 B1 · Reversed bias compensation for sense amplifier operation

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- Number: US 10,482,931 B1
- Document ID: US10482931B1
- Status: Granted
- Kind: B1
- Application number: 16/137,175
- Filed: 2018-09-20
- Granted: 2019-11-19
- Earliest claimed: 2018-09-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Shinichi Miyatake
- Web page: https://patentgrep.com/patent/US10482931B1

## CPC

- G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.

## Claims

### Claim 1

An apparatus comprising:
first and second signal lines;
a first transistor coupled between the first signal line and a first common source line, wherein a first gate of the first transistor is coupled to a biasing circuit; and
a second transistor coupled to the second signal line and the first common source line, wherein a second gate of the second transistor is coupled to the biasing circuit;
wherein the biasing circuit is configured to:
couple to the first gate of the first transistor to the second signal line and the second gate of the second transistor to the first signal line in a first configuration; and
couple the first gate of the first transistor and the second gate of the second transistor to a first voltage line in a second configuration.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the biasing circuit comprises:
a third transistor coupled between the second signal line and the first gate of the first transistor, wherein a third gate of the third transistor is coupled to a first control node;
a fourth transistor coupled between the first signal line and the second gate of the second transistor, wherein a fourth gate of the fourth transistor is coupled to the first control node;
a fifth transistor coupled between the first gate of the first transistor and the first voltage line, wherein a fifth gate of the fifth transistor is coupled to a second control node; and
a sixth transistor coupled between the second gate of the second transistor and the first voltage line, wherein a sixth gate of the sixth transistor is coupled to the second control node.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first and second control nodes are configured to control the third, fourth, fifth, and sixth transistors such that:
the third transistor and the fourth transistor are rendered conductive in the first configuration; and
the fifth transistor and the sixth transistor are rendered conductive in the second configuration during a compensation phase.

### Claim 4 (depends on 3)

The apparatus of claim 3, comprising a switch that comprises a seventh transistor coupled between the first common source line and a first power supply line, wherein a voltage of the first power supply line is configured to reverse bias the first transistor and the second transistor during the compensation phase.

### Claim 5 (depends on 1)

The apparatus of claim 1, comprising a third transistor coupled between the first common source line and a second power supply line.

### Claim 6 (depends on 1)

The apparatus of claim 1, comprising pre-charge circuitry comprising a third transistor coupled between the first signal line and the second signal line.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the pre-charge circuitry comprises a fourth transistor coupled between the first signal line and a pre-charge voltage line.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the pre-charge circuitry comprises a fourth transistor coupled between the second signal line and a pre-charge voltage line.

### Claim 9 (depends on 1)

The apparatus of claim 1, comprising a flip-flop circuitry comprising:
the first transistor;
the second transistor;
a third transistor coupled between the first signal line and a second common source line, wherein a third gate of the third transistor is coupled to the second signal line; and
a fourth transistor coupled between the second signal line and the second common source line, wherein a fourth gate of the fourth transistor is coupled to the first signal line.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the first and second transistors comprise an n-type metal-oxide semiconductor (NMOS) transistor, and the third and fourth transistors comprise a p-type metal-oxide semiconductor (PMOS) transistor.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the first signal line is coupled to a first plurality of memory cells and is configured to serve as a true bit line and wherein the second signal line is coupled to a second plurality of memory cells and is configured to serve as a complementary bit line.

### Claim 12

A memory device, comprising:
a first plurality of memory cells and a second plurality of memory cells; and
a sense amplify circuit coupled to the first plurality of memory cells through a first data line and coupled to the second plurality of memory cells through a second data line, wherein the sense amplify circuit comprises a biasing circuit and a flip-flop, wherein the flip-flop comprises:
a first transistor coupled between the first data line and a first common source line, wherein a first gate of the first transistor is coupled to a first output of the biasing circuit; and
a second transistor coupled between the second data line and the first common source line, wherein a second gate of the second transistor is coupled to a second output of the biasing circuit; and
wherein the biasing circuit is configured to:
couple the second data line to the first output of the biasing circuit and couple the first data line to the second output of the biasing circuit during a readout phase; and
couple a first voltage line to the first output of the biasing circuit and couple the first voltage line to the second output of the biasing circuit during a compensation phase.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the first common source line is configured to provide a first voltage during the compensation phase that is configured to reverse bias the first transistor and the second transistor.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the first data line and the second data line are set to a pre-charge voltage prior to the compensation phase, and wherein the first voltage line comprises a first voltage sufficiently higher than the pre-charge voltage to turn on the first transistor and the second transistor during the compensation phase.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the sense amplify circuit comprises a first pre-charge and equalizer circuitry that is configured to pre-charge the first and the second data line to the pre-charge voltage.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the sense amplify circuit comprises a switching circuitry coupled to the first voltage line and configured to provide the pre-charge voltage prior to the compensation phase or the first voltage during the compensation phase.

### Claim 17

A memory device comprising:
first and second data lines, wherein the first data line is coupled to a memory cell;
a flip-flop comprising:
a first transistor comprising a first source terminal coupled to the first data line, a first gate terminal coupled to a first output of a biasing circuit and a first drain terminal coupled to a first common source line; and
a second transistor comprising a second source terminal coupled to the second data line, a second gate terminal coupled to a second output of the biasing circuit and a second drain terminal coupled to the first common source line; and
reversed bias compensation circuitry comprising the biasing circuit, a pre-charge circuitry, wherein the reversed bias compensation circuitry is configured to:
pre-charge and equalize the first data line and the second data line to a pre-charge voltage using the pre-charge circuitry;
during a compensation phase, connect the first gate terminal and the second gate terminal to a first voltage higher than the pre-charge voltage using the biasing circuit; and
during a readout phase, connect the first gate terminal to the second data line and the second gate terminal to the first data line and connect the memory cell to the first data line; and
wherein the compensation phase is configured to generate a first voltage difference between the first data line and the second data line that is proportional to a difference ΔVth between a first gate-source threshold voltage of the first transistor and a second gate-source threshold voltage of the second transistor.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the reversed bias compensation circuitry comprises a switch coupled to the first common source line, and wherein during the compensation phase, the switch is configured to provide a second voltage that reverse biases the first transistor and the second transistor.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the compensation phase comprises a first duration configured to cause the first voltage difference is to become a product between a proportionality factor α and the difference ΔVth, and wherein the proportionality factor α is based, in part, on the first duration.

### Claim 20 (depends on 19)

The memory device of claim 19, comprising a trip voltage (Vtrip) specification that is based on the proportionality factor α, wherein the flip-flop is configured to sense a voltage difference between the first data line and the second data line that is larger than the Vtrip specification.

### Claim 21

A memory device comprising a sense amplifier configured to sense a voltage difference between first and second signal lines, wherein the sense amplifier comprises:
a first transistor coupled between the first signal line and a first power node, the first transistor having a first gate coupled to a first circuit node;
a second transistor coupled between the second signal line and the first power node, the second transistor having a second gate coupled to a second circuit node;
a third transistor coupled between the second signal line and the first circuit node, the third transistor having a third gate coupled to a first control node;
a fourth transistor coupled between the first signal line and the second circuit node, the fourth transistor having a fourth gate coupled to the first control node;
a fifth transistor coupled between the first circuit node and a second power node, the fifth transistor having a fifth gate coupled to a second control node; and
a sixth transistor coupled between the second circuit node and the second power node, the sixth transistor having a sixth gate coupled to the second control node.

### Claim 22 (depends on 21)

The memory device of claim 21, further comprising:
a seventh transistor coupled between the first power node and a first power supply line; and
an eighth transistor coupled between the first power node and a second power supply line.

### Claim 23 (depends on 21)

The memory device of claim 21, further comprising:
a seventh transistor coupled between the first signal line and a third power node, the seventh transistor having a seventh coupled to the second signal line; and
a eight transistor coupled between the second signal line and the third power node, the eight transistor having an eight gate coupled to the first signal line.

### Claim 24 (depends on 23)

The memory device of claim 23, wherein each of the first and second transistors is of a first channel type and each of the seventh and eight transistors is of a second channel type.

### Claim 25 (depends on 21)

The memory device of claim 21, wherein the first and second control nodes are configured to control the first, second, third and fourth transistors such that:
the third transistor and fourth transistor are rendered conductive while the first and second transistors are rendered non-conductive during a first operation phase; and
the first transistor and second transistor are rendered conductive while the third and fourth transistors are rendered non-conductive during a second operation phase following the first operation phase.

### Claim 26 (depends on 25)

The memory device of claim 25, wherein the first signal line is coupled to a plurality of memory cells to serve as a true bit line and the second signal line is coupled to a plurality of different memory cells to serve as a complementary bit line.