# US 10,482,930 B2 · Memory chip with reduced power consumption, buffer chip module controlling the same and memory module including the same

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- Number: US 10,482,930 B2
- Document ID: US10482930B2
- Status: Granted
- Kind: B2
- Application number: 15/926,638
- Filed: 2018-03-20
- Published: 2019-03-21
- Granted: 2019-11-19
- Earliest claimed: 2017-09-21
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Young-Suk Moon
- Web page: https://patentgrep.com/patent/US10482930B2

## CPC

- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G06F 13/1673: {using buffers}
- G06F 13/4278: {using an embedded synchronisation}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/109: {Control signal input circuits}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/417: for memory cells of the field-effect type
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 2207/2227: Standby or low power modes
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.

## Claims

### Claim 1

A memory chip, comprising:
a chip select (CS) buffer configured to receive a chip select signal;
a chip identification (CID) buffer configured to receive a chip identification signal; and
a command (CMD) buffer configured to receive a command signal,
wherein the chip identification signal is input after a time has elapsed since the chip select signal is activated and before the command signal is input and the CID buffer is activated when the chip identification signal is input, and
wherein the command signal is input after a time has elapsed since the identification signal is input and the CMD buffer is activated when the command signal is input.

### Claim 2 (depends on 1)

The memory chip of claim 1, further comprising an address (ADDR) buffer configured to receive an address signal wherein the address signal is input after a time has elapsed since the command signal is input and the ADDR buffer is activated when the address signal is input.

### Claim 3 (depends on 1)

The memory chip of claim 1, wherein the CMD buffer and the ADDR buffer maintains an off state when the chip select signal and the chip identification signal do not correspond to the memory chip.

### Claim 4 (depends on 1)

The memory chip of claim 1, further comprising:
a buffer activation controller configured to control activation of the CID buffer, the CMD buffer, and an address (ADDR) buffer.

### Claim 5 (depends on 4)

The memory chip of claim 4, further comprising:
a configuration register configured to store timing information about the activation of the CMD buffer and the ADDR buffer,
wherein the buffer activation controller controls activation of the CID buffer, the CMD, buffer and the ADDR buffer based on the timing information about the activation of the CMD buffer and the ADDR buffer.

### Claim 6

A buffer chip module, comprising:
a control signal queue configured to receive a control signal divided into a chip select signal, a chip identification signal, a command signal, and an address signal, and to store the chip select signal, the command signal, and the address signal; and
an arbiter configured to output the divided control signal stored in the control signal queue according to a predetermined timing condition,
wherein the arbiter outputs the chip identification signal before outputting the command signal and after the chip select signal is activated.

### Claim 7 (depends on 6)

The buffer chip module of claim 6, wherein the arbiter outputs the address signal after a time has elapsed since the command signal is output.

### Claim 8 (depends on 6)

The buffer chip module of claim 6, further comprising:
a host interface configured to transmit or receive a signal to and from a memory controller or a host;
a control signal input circuit configured to divide and store the control signal in the control signal queue;
a memory interface configured to transmit or receive a signal between the arbiter and a memory chip or a memory module including the memory chip; and
a data buffer configured to buffer data between the host interface and the memory interface.

### Claim 9

A memory module, comprising:
a plurality of memory chips each including a chip select (CS) buffer buffering a chip select signal, a chip identification (CID) buffer buffering a chip identification signal, a command (CMD) buffer buffering a command signal and an address (ADDR) buffer buffering an address signal; and
a buffer chip module configured to output the chip select signal, the chip identification signal, the command signal, and the address signal to the plurality of memory chips,
wherein the buffer chip module outputs the chip identification signal before outputting the command signal and after a predetermined time has elapsed since the chip select signal is activated, and a CMD buffer and an ADDR buffer, included in a memory chip among the plurality of memory chips, are de-activated before the chip select signal is activated and before the chip identification signal is output.

### Claim 10 (depends on 9)

The memory module of claim 9, wherein a CMD buffer and an ADDR buffer included in a memory chip among the plurality of memory chips that does not correspond to the chip select signal and the chip identification signal are de-activated.

### Claim 11 (depends on 10)

The memory module of claim 10, wherein the buffer chip module outputs the command signal after a predetermined time has elapsed since the chip identification signal is output, and the memory chip among the plurality of memory chips that corresponds to the chip select signal and the chip identification signal activates a CMD buffer therein when the command signal is input.

### Claim 12 (depends on 11)

The memory module of claim 11, wherein the buffer chip module outputs the address signal after a predetermined time has elapsed since the command signal is output, and the memory chip among the plurality of memory chips that corresponds to the chip select signal and the chip identification signal activates an ADDR buffer in the memory chip when the address signal is input.

### Claim 13 (depends on 11)

The memory module of claim 11, wherein each of the plurality of memory chips further comprises a buffer activation controller configured to control activation of a CS buffer, a CID buffer, a CMD buffer and an ADDR buffer of the memory chip.

### Claim 14 (depends on 11)

The memory module of claim 11, wherein each of the plurality of memory chips further comprises a configuration register configured to store in the configuration register timing information about activation of a CS buffer, a CID buffer, a CMD buffer and an ADDR buffer and the buffer activation controller controls activation referring to the configuration register.

### Claim 15 (depends on 9)

The memory module of claim 9, wherein the buffer chip module comprises:
a control signal queue configured to divide the control signal into the chip select signal, the chip identification signal, the command signal, the address signal and to store the chip select signal, the chip identification signal, the command signal and the address signal; and
an arbiter configured to output the divided control signal stored in the control signal queue according to a predetermined timing condition.

### Claim 16 (depends on 15)

The memory module of claim 15, wherein the buffer chip module comprises:
a host interface configured to transmit or receive a signal to and from a memory controller or a host;
a control signal input circuit configured to divide and store the control signal in the control signal queue;
a memory interface configured to transmit or receive a signal between the arbiter and a memory chip or a memory module including the memory chip; and
a data buffer configured to buffer data between the host interface and the memory interface.

### Claim 17 (depends on 9)

The memory module of claim 9, wherein the plurality of memory chips are included in a single semiconductor chip.