# US 10,482,921 B2 · Error detection code hold pattern synchronization

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- Number: US 10,482,921 B2
- Document ID: US10482921B2
- Status: Granted
- Kind: B2
- Application number: 16/262,661
- Filed: 2019-01-30
- Published: 2019-05-30
- Granted: 2019-11-19
- Earliest claimed: 2017-05-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Stefan Dietrich
- Web page: https://patentgrep.com/patent/US10482921B2

## CPC

- G11B 20/18: Error detection or correction; Testing {, e.g. of drop-outs}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11B 2020/1222: {ECC block, i.e. a block of error correction encoded symbols which includes all parity data needed for decoding}
- G11B 2020/1843: {using a cyclic redundancy check [CRC]}
- G11C 2029/0411: {Online error correction}
- G11C 2029/1204: {Bit line control}
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

## Claims

### Claim 1

A method, comprising:
detecting a first scenario, comprising an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both;
upon detection of the first scenario:
asserting an error detection code (EDC) hold reset; and
de-asserting the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to a data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 2 (depends on 1)

The method of claim 1, comprising:
detecting an occurrence of the falling edge of the EDC hold reset;
triggering the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 3 (depends on 1)

The method of claim 1, wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.

### Claim 4 (depends on 1)

The method of claim 1, wherein the memory device comprises dynamic random-access memory (DRAM).

### Claim 5 (depends on 1)

The method of claim 1, comprising:
transmitting the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the WCK_t frequency is twice the CK_t frequency.

### Claim 7 (depends on 1)

The method of claim 1, comprising asserting the error detection code (EDC) hold reset, via EDC hold pattern generation circuitry, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.

### Claim 8

An electronic device, comprising:
a command clock (CK_t clock);
a data path clock (WCK_t);
error detection code (EDC) hold pattern generation circuitry, configured to:
upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
assert an EDC hold reset; and
de-assert the EDC hold reset synchronous to a rising edge of the command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 9 (depends on 8)

The electronic device of claim 8, comprising:
detecting an occurrence of the falling edge of the EDC hold reset;
triggering the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 10 (depends on 8)

The electronic device of claim 8, comprising the memory device, wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.

### Claim 11 (depends on 8)

The electronic device of claim 8, comprising the memory device, wherein the memory device comprises dynamic random-access memory (DRAM).

### Claim 12 (depends on 8)

The electronic device of claim 8, comprising the memory device, wherein the electronic device is configured to transmit the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.

### Claim 13 (depends on 8)

The electronic device of claim 8, wherein the WCK_t frequency is twice the CK_t frequency.

### Claim 14 (depends on 8)

The electronic device of claim 8, wherein the EDC hold pattern generation circuitry is configured to assert the error detection code (EDC) hold reset, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.

### Claim 15

An error detection code (EDC) hold pattern generation circuitry, configured to:
upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
assert an EDC hold reset; and
de-assert the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 16 (depends on 15)

The EDC hold pattern generation circuitry of claim 15, configured to:
detect an occurrence of the falling edge of the EDC hold reset;
trigger the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.

### Claim 17 (depends on 15)

The EDC hold pattern generation circuitry of claim 15, wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.

### Claim 18 (depends on 15)

The EDC hold pattern generation circuitry of claim 15, wherein the memory device comprises dynamic random-access memory (DRAM).

### Claim 19 (depends on 15)

The EDC hold pattern generation circuitry of claim 15, configured to transmit the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.

### Claim 20 (depends on 15)

The EDC hold pattern generation circuitry of claim 15, configured to assert the error detection code (EDC) hold reset, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.