# US 10,482,826 B2 · GOA driving circuits and display devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,826 B2 - Document ID: US10482826B2 - Status: Granted - Kind: B2 - Application number: 15/328,478 - Filed: 2017-01-12 - Published: 2018-11-22 - Granted: 2019-11-19 - Earliest claimed: 2016-12-30 - Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Inventors: Longqiang Shi - Web page: https://patentgrep.com/patent/US10482826B2 ## CPC - G09G 3/34: by control of light from an independent source - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - H10H 20/80: Constructional details - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract The present disclosure relates to a GOA driving circuit including N number of cascaded GOA units, wherein N is a natural number not smaller than four. The GOA unit at the i-th level includes a first controllable transistor (T1), a second controllable transistor (T2), a third controllable transistor (T3), a first capacitor (C1), and a first pull-down maintain unit, wherein 1≤i≤a and “a” is a natural number smaller than or equal to N/2. The GOA unit at the j-th level includes a fourth controllable transistor (T4), a fifth controllable transistor (T5), a second capacitor (C2), and a second pull-down maintain unit 20, wherein a+1≤j≤N. The GOA driving circuit may reduce the line buffer so as to reduce the cost of the GOA driving circuit. ## Claims ### Claim 1 A gate driver on array (GOA) driving circuit, comprising: N number of cascaded-connected GOA units, wherein N is a natural number not smaller than four, wherein the GOA unit at the i-th level comprises a first transistor, a second transistor; a third transistor, a first capacitor, and a first pull-down maintain unit, wherein 1≤i≤a and a is a natural number smaller than or equal to N/2; a source and a gate of the first transistor receives turn-on signals, and a drain of the first transistor respectively connects to the first pull-down maintain unit and a node at the i-th level; a source of the second transistor receives the turn-on signals, a gate of the second transistor receives second clock signals, and a drain of the second transistor connects to the node at the i-th level; a source of the third transistor receives first clock signals, a gate of the third transistor connects to the node at the i-th level, and a drain of the third transistor respectively connects to the other end of the first capacitor and a gate signal output end at the i-th level; one end of the first capacitor connects to the node at the i-th level, and the other end of the first capacitor connects to the first pull-down maintain unit, the first pull-down maintain unit connects to a direct-current low voltage end; the GOA unit at the j-th level comprises a fourth transistor, a fifth transistor, a second capacitor, and a second pull-down maintain unit, wherein a+1≤j≤N; a source of the fourth transistor connects to a gate signal output end in the (j−a)-th level, a gate of the fourth transistor receives the second clock signals, a drain of the fourth transistor respectively connects to second pull-down maintain unit and the node at the j-th level Q(j); a source of the fifth transistor receives the first clock signals, a gate of the fifth transistor connects to the node at the j-th level Q(j), and a drain of the fifth transistor respectively connects to the other end of the second capacitor and the gate signal output end at the j-th level; and one end of the second capacitor connects to the node in the j-th level, and the other end of the second capacitor connects to the second pull-down maintain unit, and the second pull-down maintain unit connects to a turn-off voltage; and wherein the second clock signals and the first clock signals are two different clock signals in one clock signals set; the clock signals set comprises M number of clock signals, wherein M is a positive integer, wherein a period of each of the clock signals is 8H, and a high level duration of each of the clock signals is 3.2H, a rising edge of the (m+1)-th clock signals is delayed by a time delay of the rising edge of the m-th clock signals, wherein m is a positive integer in a range from 1 to M, and m is not equal to three, the rising edge of the third clock signals is delayed by 1.2H of the rising edge of the second clock signals. ### Claim 2 (depends on 1) The GOA driving circuit as claimed in claim 1, wherein a waveform of the second clock signals is opposite to the waveform of the first clock signals. ### Claim 3 (depends on 2) The GOA driving circuit as claimed in claim 2, wherein “a” equals to 4. ### Claim 4 (depends on 2) The GOA driving circuit as claimed in claim 2, wherein the second clock signals and the first clock signals are two different clock signals in one clock signals set; the clock signals set comprises M number of clock signals, wherein M is a positive integer, wherein a period of each of the clock signals is 8H, and a high level duration of each of the clock signals is 3.2H, a rising edge of the (m+1)-th clock signals is delayed by a time delay of the rising edge of the m-th clock signals, wherein m is a positive integer in a range from 1 to M, and m is not equal to three, the rising edge of the third clock signals is delayed by 1.2H of the rising edge of the second clock signals. ### Claim 5 (depends on 4) The GOA driving circuit as claimed in claim 4, wherein a high level duration of the turn-on signals is 4H, and the rising edge of the fourth clock signals is delayed by the time delay of the rising edge of the turn-on signals. ### Claim 6 (depends on 5) The GOA driving circuit as claimed in claim 5, wherein a high level duration of first gate signals outputted by the gate signal output end at the first level is 4.2H, and the first rising edge of data voltage signals is delayed by 3.5H of the rising edge of the turn-on signals. ### Claim 7 (depends on 6) The GOA driving circuit as claimed in claim 6, wherein when the turn-on signals are at the high level, the first transistor is turned on, a high level of the turn-on signals is transmitted to the node at the first level, and the node at the first level is at the high level; the third transistor is turned on, the first clock signals are at the low level, and the gate signal output end at the first level is at the low level; the first clock signals transit from the low level to the high level, the gate signal output end at the first level is at the high level, and the node at the first level is raised up to a higher level due to a capacitance coupling effect; the second clock signals are at the high level, the first transistor is turned on, the first clock signals are at the low level, the gate signal output end at the first level is pulled down to the low level, and the low level signals of the turn-on signals are transmitted to the node at the first level via the turned-on first transistor, and the node at the first level is pulled down to the low level. ### Claim 8 (depends on 6) The GOA driving circuit as claimed in claim 6, wherein when the gate signal output end in the (j−a)-th level is at the high level, the second clock signals are at the high level, the fourth transistor is turned on, the high level of the gate signal output end in the (j−a)-th level is transmitted to the node at the j-th level, and the node at the j-th level is at the high level; the fifth transistor is turned on, the first clock signals are at the low level, the gate signal output end at the j-th level is at the low level; the gate signal output end in the (j−a)-th level is at the low level, the second clock signals are at the low level, the fourth transistor is turned off; the first clock signals are at the high level, the gate signal output end at the j-th level is at the high level, the level of the node at the j-th level is raised up to a higher level due to the capacitance coupling effect; the first clock signals are at the low level, the gate signal output end at the j-th level is pulled down to the low level, the second clock signals are at the high level, the low level of the gate signal output end at the (j−a)-th level is transmitted to the node in the j-th level, and the node in the j-th level is pulled down to the low level. ### Claim 9 (depends on 1) The GOA driving circuit as claimed in claim 1, wherein “a” equals to 4. ### Claim 10 (depends on 1) The GOA driving circuit as claimed in claim 1, wherein a high level duration of the turn-on signals is 4H, and the rising edge of the fourth clock signals is delayed by the time delay of the rising edge of the turn-on signals. ### Claim 11 (depends on 10) The GOA driving circuit as claimed in claim 10, wherein a high level duration of first gate signals outputted by the gate signal output end at the first level is 4.2H, and the first rising edge of data voltage signals is delayed by 3.5H of the rising edge of the turn-on signals. ### Claim 12 (depends on 11) The GOA driving circuit as claimed in claim 11, wherein when the turn-on signals are at the high level, the first transistor is turned on, a high level of the turn-on signals is transmitted to the node at the first level, and the node at the first level is at the high level; the third transistor is turned on, the first clock signals are at the low level, and the gate signal output end at the first level is at the low level; the first clock signals transit from the low level to the high level, the gate signal output end at the first level is at the high level, and the node at the first level is raised up to a higher level due to a capacitance coupling effect; the second clock signals are at the high level, the first transistor is turned on, the first clock signals are at the low level, the gate signal output end at the first level is pulled down to the low level, and the low level signals of the turn-on signals are transmitted to the node at the first level via the turned-on first transistor, and the node at the first level is pulled down to the low level. ### Claim 13 (depends on 11) The GOA driving circuit as claimed in claim 11, wherein when the gate signal output end in the (j−a)-th level is at the high level, the second clock signals are at the high level, the fourth transistor is turned on, the high level of the gate signal output end in the (j−a)-th level is transmitted to the node at the j-th level, and the node at the j-th level is at the high level; the fifth transistor is turned on, the first clock signals are at the low level, the gate signal output end at the j-th level is at the low level; the gate signal output end in the (j−a)-th level is at the low level, the second clock signals are at the low level, the fourth transistor is turned off; the first clock signals are at the high level, the gate signal output end at the j-th level is at the high level, the level of the node at the j-th level is raised up to a higher level due to the capacitance coupling effect; the first clock signals are at the low level, the gate signal output end at the j-th level is pulled down to the low level, the second clock signals are at the high level, the low level of the gate signal output end at the (j−a)-th level is transmitted to the node in the j-th level, and the node in the j-th level is pulled down to the low level. ### Claim 14 (depends on 1) A display device comprises the GOA driving circuit as claimed in claim 1.