# US 10,482,807 B2 · Interface devices and liquid crystal devices with the same

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- Number: US 10,482,807 B2
- Document ID: US10482807B2
- Status: Granted
- Kind: B2
- Application number: 15/129,922
- Filed: 2016-07-19
- Published: 2018-08-02
- Granted: 2019-11-19
- Earliest claimed: 2016-05-31
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Zhao Wang; Yu-yeh Chen; Yin-hung Chen; Yu Wu
- Web page: https://patentgrep.com/patent/US10482807B2

## CPC

- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G09G 3/36: using liquid crystals
- G09G 2320/0686: with two or more screen areas displaying information with different brightness or colours
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure relates to an interface device for high resolution liquid crystal device (LCD). The interface device includes a first connector configured to receive low voltage differential signals (LVDS) provided for a left-half active area of the LCD, a second connector configured to receive the LVDS provided for a right-half active area of the LCD, and a third connector configured to receive operational voltage signals and control signals provided for the LCD. The present disclosure also relates to a LCD with the above interface device. With such configuration, the data signals and the control signals are not mixed to enhance the signal quality, and the display performance of the LCD may not be affected.

## Claims

### Claim 1

An interface device for high resolution liquid crystal device (LCD), comprising:
a first connector configured to receive low voltage differential signals (LVDS) provided for a left-half active area of the LCD, a second connector configured to receive the LVDS provided for a right-half active area of the LCD, and a third connector configured to receive operational voltage signals and control signals provided for the LCD;
wherein the left-half active area comprises N number of left active areas along a direction from left to right in sequence, and each of the left active areas correspond to one left-positive-negative-pole-pin pair, the first connector comprises N number of left-positive-negative-pole-pin pairs, each of the left-positive-negative-pole-pin pairs comprises a first-left grounding pin, a left-positive-pole-pin and a left-negative-pole-pin, and the first-left grounding pin directly followed by the left-positive-pole-pin directly followed by the left-negative-pole-pin, each of the left-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding left active area, and each of the left-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding left active area; and
wherein the first connector further comprises at least one no-load (NC) pin before the N number of left-positive-negative-pole-pin pairs, and a second-left grounding pin after the N number of left-positive-negative-pole-pin pairs.

### Claim 2 (depends on 1)

The interface device as claimed in claim 1, wherein the right-half active area comprises N number of right active areas along a direction from left to right in sequence, and each of the right active areas correspond to one right-positive-negative-pole-pin pair, the second connector comprises N number of right-positive-negative-pole-pin pairs, each of the right-positive-negative-pole-pin pairs comprises a first-right grounding pin, a right-positive-pole-pin and a right-negative-pole-pin, and the first-right grounding pin directly followed by the right-positive-pole-pin directly followed by the right-negative-pole-pin, each of the right-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding right active area, and each of the right-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding right active area.

### Claim 3 (depends on 2)

The interface device as claimed in claim 2, wherein the second connector further comprises at least one NC pin before the N number of the right-positive-negative-pole-pin pairs, and a second-right grounding pin after the N number of right-positive-negative-pole-pin pairs.

### Claim 4 (depends on 1)

The interface device as claimed in claim 1, wherein the third connector comprises a plurality of voltage pins and a plurality of signal control pins arranged in sequence, each of the voltage pins is configured to receive the operational voltage signals for the LCD, and each of the signal control pins is configured to receive the control signals for the LCD.

### Claim 5 (depends on 3)

The interface device as claimed in claim 3, wherein the third connector comprises a plurality of voltage pins and a plurality of signal control pins arranged in sequence, each of the voltage pins is configured to receive the operational voltage signals for the LCD, and each of the signal control pins is configured to receive the control signals for the LCD.

### Claim 6 (depends on 4)

The interface device as claimed in claim 4, wherein the third connector further comprises at least one NC pin and at least one grounding pin arranged between the voltage pins and the signal control pins in sequence.

### Claim 7

A liquid crystal device (LCD), comprising:
an interface device comprises a first connector configured to receive low voltage differential signals (LVDS) provided for a left-half active area of the LCD, a second connector configured to receive the LVDS provided for a right-half active area of the LCD, and a third connector configured to receive operational voltage signals and control signals provided for the LCD;
wherein the left-half active area comprises N number of left active areas along a direction from left to right in sequence, and each of the left active areas correspond to one left-positive-negative-pole-pin pair, the first connector comprises N number of left-positive-negative-pole-pin pairs, each of the left-positive-negative-pole-pin pairs comprises a first-left grounding pin, a left-positive-pole-pin and a left-negative-pole-pin, and the first-left grounding pin directly followed by the left-positive-pole-pin directly followed by the left-negative-pole-pin, each of the left-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding left active area, and each of the left-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding left active area;
wherein the first connector further comprises at least one no-load (NC) pin before the N number of left-positive-negative-pole-pin pairs, and a second-left grounding pin after the N number of left-positive-negative-pole-pin pairs; and
wherein the right-half active area comprises N number of right active areas along a direction from left to right in sequence, and each of the right active areas correspond to one right-positive-negative-pole-pin pair, the second connector comprises N number of right-positive-negative-pole-pin pairs, each of the right-positive-negative-pole-pin pairs comprises a first-right grounding pin, a right-positive-pole-pin and a right-negative-pole-pin, and the first-right grounding pin directly followed by the right-positive-pole-pin directly followed by the right-negative-pole-pin, each of the right-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding right active area, and each of the right-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding right active area.