# US 10,482,593 B2 · Inspection method, inspection system, and method of manufacturing semiconductor package using the same

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- Number: US 10,482,593 B2
- Document ID: US10482593B2
- Status: Granted
- Kind: B2
- Application number: 15/626,675
- Filed: 2017-06-19
- Published: 2018-01-04
- Granted: 2019-11-19
- Earliest claimed: 2016-07-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Younghoon Sohn; Yusin Yang
- Web page: https://patentgrep.com/patent/US10482593B2

## CPC

- G06T 7/0008: {checking presence/absence}
- G06T 7/001: {using an image reference approach}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- G06T 2207/30148: Semiconductor; IC; Wafer
- H10P 74/27: {Structural arrangements therefor}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/10: characterised by their shape or disposition
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An inspection method includes generating first layout data including information on a shape of a first pattern group, generating second layout data including information on a shape of a second pattern group, obtaining a target image including images of the first and second pattern groups, and detecting a defect pattern from the target image by comparing the first and second layout data with the target image. The first pattern group, the second pattern group, and the defect pattern are provided at different heights from each other, from a top surface of a substrate.

## Claims

### Claim 1

A method of manufacturing a semiconductor package, the method comprising:
forming a first pattern group on a substrate;
measuring a first image of the first pattern group to generate first layout data based on the first image;
forming an interlayer layer on the first pattern group;
forming a second pattern group on the interlayer layer;
measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer;
measuring a third image including the first image and the second image to generate third layout data based on the third image; and
detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

### Claim 2 (depends on 1)

The method of claim 1, wherein
the defect pattern is in the interlayer layer between the first pattern group and the second pattern group, and
the third image includes an image of the defect pattern.

### Claim 3 (depends on 2)

The method of claim 2, wherein the detecting of the defect pattern comprises:
comparing the third layout data with the first layout data and the second layout data; and
selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

### Claim 4 (depends on 1)

The method of claim 1, wherein
the first image and the second image are obtained using a first optical system,
the third image is obtained using a second optical system, and
the second optical system has a depth of focus greater than that of the first optical system.

### Claim 5 (depends on 1)

The method of claim 1, wherein
the first image and the second image are obtained using a first optical system including a first light source, and
the third image is obtained using a second optical system including a second light source different from the first light source.

### Claim 6 (depends on 5)

The method of claim 5, wherein
a first light of the first light source is incident in a direction inclined to a top surface of the substrate, and
a second light of the second light source is incident in a direction vertical to the top surface of the substrate.

### Claim 7 (depends on 5)

The method of claim 5, wherein
the first optical system is a dark-field illumination system, and
the second optical system is a bright-field illumination system.

### Claim 8

A method of manufacturing a semiconductor package, the method comprising:
forming a first pattern group on a substrate;
measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source;
forming an interlayer layer on the first pattern group;
forming a second pattern group on the interlayer layer;
measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;
measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source different from the first light source; and
detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

### Claim 9 (depends on 8)

The method of claim 8, wherein the detecting of the defect pattern comprises:
comparing the third layout data with the first layout data and the second layout data; and
selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

### Claim 10 (depends on 8)

The method of claim 8, wherein the substrate comprises:
a support substrate including a plurality of cavities penetrating the support substrate;
semiconductor chips in the plurality of cavities; and
a mold layer on a first surface of the support substrate to cover the semiconductor chips, the mold layer extending into the cavities such that the mold layer is between the support substrate and the semiconductor chips, wherein
the first pattern group, the second pattern group, and the defect pattern are on a second surface of the support substrate, the second surface being opposite the first surface.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
the first and second pattern groups include interconnection line patterns, the interconnection line patterns configured to electrically connect the semiconductor chips to external terminals, and
the defect pattern is in a transparent or translucent insulating layer between the first pattern group and the second pattern group.

### Claim 12 (depends on 8)

The method of claim 8, wherein a first light of the first light source is incident in a direction inclined to a top surface of the substrate.

### Claim 13 (depends on 8)

The method of claim 8, wherein a second light of the second light source is incident in a direction vertical to a top surface of the substrate.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first image and the second image are obtained using a first optical system including the first light source,
the third image is obtained using a second optical system including the second light source, and
the second optical system has a depth of focus greater than that of the first optical system.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first optical system is a dark-field illumination system, and the second optical system is a bright-field illumination system.

### Claim 16 (depends on 8)

The method of claim 8, wherein a first light of the first light source is incident in a direction inclined to a top surface of the substrate, and a second light of the second light source is incident in a direction vertical to a top surface of the substrate.

### Claim 17

A method of manufacturing a semiconductor package, the method comprising:
forming a first pattern group on a substrate;
measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source configuring a dark-field illumination system;
forming an interlayer layer on the first pattern group;
forming a second pattern group on the interlayer layer;
measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;
measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source configuring a bright-field illumination system; and
detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

### Claim 18 (depends on 17)

The method of claim 17, wherein the defect pattern is in the interlayer layer between the first pattern group and the second pattern group.

### Claim 19 (depends on 18)

The method of claim 18, wherein the third image includes an image of the defect pattern, and wherein the detecting of the defect pattern comprises:
comparing the third layout data with the first layout data and the second layout data; and
selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

### Claim 20 (depends on 17)

The method of claim 17, wherein the substrate comprises:
a support substrate including a plurality of cavities penetrating the support substrate;
semiconductor chips in the plurality of cavities; and
a mold layer on a first surface of the support substrate to cover the semiconductor chips, the mold layer extending into the cavities such that the mold layer is between the support substrate and the semiconductor chips, wherein
the first pattern group, the second pattern group, and the defect pattern are on a second surface of the support substrate, the second surface being opposite the first surface,
the first and second pattern groups include interconnection line patterns, the interconnection line patterns configured to electrically connect the semiconductor chips to external terminals, and
the defect pattern is in a transparent or translucent insulating layer between the first pattern group and the second pattern group.