# US 10,482,563 B2 · Method and apparatus for processing image enhancement algorithm > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,563 B2 - Document ID: US10482563B2 - Status: Granted - Kind: B2 - Application number: 15/519,318 - Filed: 2015-10-13 - Published: 2017-08-24 - Granted: 2019-11-19 - Earliest claimed: 2014-10-16 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Won-jae Lee; Min-soo Kim; Young-hwan Park - Web page: https://patentgrep.com/patent/US10482563B2 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06T 5/00: Image enhancement or restoration - G06T 2200/28: involving image processing hardware - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Disclosed are an image enhancement algorithm processing method and apparatus. The image enhancement algorithm processing method includes setting a plurality of different control registers, indexing and storing the set plurality of control registers, calling a first control register corresponding to a first index among the stored plurality of control registers by using the first index, and commanding a hardware accelerator to perform a first function defined by the called first control register. ## Claims ### Claim 1 An image enhancement algorithm processing apparatus comprising: a hardware accelerator; a processor configured to: set a plurality of different control registers, index and store the plurality of different control registers in a buffer, call a first control register corresponding to a first index among the plurality of different control registers stored in the buffer by using the first index, and command the hardware accelerator to perform a first function defined by the called first control register; and a memory configured to be shared by the processor and the hardware accelerator, wherein data is read from the memory and is stored in the buffer, wherein a first priority is assigned to the processor and a second priority is assigned to the hardware accelerator, wherein the processor is further configured to assign the second priority of the hardware accelerator to be higher than the first priority assigned to the processor, wherein, when the processor and the hardware accelerator access the buffer, the processor and the hardware accelerator access the buffer in an order according to the assigned priorities, wherein the hardware accelerator comprises a plurality of hardware accelerators, and wherein each of the plurality of hardware accelerators comprises a priority that is higher than the first priority assigned to the processor. ### Claim 2 (depends on 1) The image enhancement algorithm processing apparatus of claim 1, wherein the plurality of different control registers define different functions. ### Claim 3 (depends on 1) The image enhancement algorithm processing apparatus of claim 1, wherein after commanding the hardware accelerator to perform the first function, the processor is further configured to call a second control register corresponding to a second index among the plurality of different control registers stored in the buffer by using the second index, and command the hardware accelerator to perform a second function defined by the called second control register, the first function being different from the second function. ### Claim 4 (depends on 3) The image enhancement algorithm processing apparatus of claim 3, wherein in the calling of the second control register, a computer program automatically converts an index, and the processor calls a control register corresponding to the index obtained through the conversion among the plurality of different control registers stored in the buffer by using the index. ### Claim 5 (depends on 3) The image enhancement algorithm processing apparatus of claim 3, wherein the hardware accelerator is configured to: receive a command defined by the second control register, and perform the second function. ### Claim 6 (depends on 1) The image enhancement algorithm processing apparatus of claim 1, wherein the hardware accelerator is configured to: receive a command defined by the first control register, and perform the first function. ### Claim 7 An image enhancement algorithm processing apparatus comprising: a hardware accelerator; a processor configured to: set a control register defining a second function while the hardware accelerator is performing a first function, index and store the set control register in a buffer, and after the hardware accelerator performs the first function, command the hardware accelerator to perform the second function defined by the set control register; and a memory configured to be shared by the processor and the hardware accelerator, wherein data is read from the memory and is stored in the buffer, wherein a first priority is assigned to the processor and a second priority is assigned to the hardware accelerator, wherein the processor is further configured to assign the second priority of the hardware accelerator to be higher than the first priority assigned to the processor, wherein, when the processor and the hardware accelerator access the buffer, the processor and the hardware accelerator access the buffer in an order according to the assigned priorities, wherein the hardware accelerator comprises a plurality of hardware accelerators, and wherein each of the plurality of hardware accelerators comprises a priority that is higher than the first priority assigned to the processor. ### Claim 8 An image enhancement algorithm processing method performed by a processor, the image enhancement algorithm processing method comprising: setting a plurality of different control registers; indexing and storing the plurality of different control registers in a buffer; calling a first control register corresponding to a first index among the plurality of different control registers stored in the buffer by using the first index; commanding a hardware accelerator to perform a first function defined by the called first control register; storing data read from a memory shared by the processor and the hardware accelerator, in the buffer; assigning a first priority to the processor and a second priority to the hardware accelerator; and accessing the buffer in an order according to the assigned priorities, in response to the processor and the hardware accelerator accessing the buffer, wherein the assigning of the first and second priorities comprises assigning the second priority of the hardware accelerator to be higher than the first priority assigned to the processor, wherein the hardware accelerator comprises a plurality of hardware accelerators, and wherein each of the plurality of hardware accelerators comprises a priority that is higher than the first priority assigned to the processor. ### Claim 9 (depends on 8) The image enhancement algorithm processing method of claim 8, further comprising: calling a second control register corresponding to a second index among the plurality of different control registers stored in the buffer by using the second index; and commanding the hardware accelerator to perform a second function defined by the called second control register, wherein the first function differs from the second function. ### Claim 10 (depends on 9) The image enhancement algorithm processing method of claim 9, wherein the calling of the second control register comprises: automatically converting, by a computer program, an index; and calling, by the processor, a control register corresponding to the index obtained through the conversion among the plurality of different control registers stored in the buffer by using the index. ### Claim 11 (depends on 8) A non-transitory computer-readable storage medium storing a program for executing the image enhancement algorithm processing method of claim 8 in a computer.