# US 10,482,290 B1 · Virtual polymorphic hardware engine

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- Number: US 10,482,290 B1
- Document ID: US10482290B1
- Status: Granted
- Kind: B1
- Application number: 16/193,424
- Filed: 2018-11-16
- Granted: 2019-11-19
- Earliest claimed: 2016-07-11
- Assignees: Cipherloc Corporation
- Applicants: Cipherloc Corporation
- Inventors: Albert Henry Carlson; Robert LeBlanc
- Web page: https://patentgrep.com/patent/US10482290B1

## CPC

- G06F 21/75: by inhibiting the analysis of circuitry or operation
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/002: {Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441)}
- G06F 2221/2125: Just-in-time application of countermeasures, e.g., on-the-fly decryption, just-in-time obfuscation or de-obfuscation
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Virtual field programmable gate array (VFPGA) duplicates and/or emulates a field programmable gate array through the use of base hardware and firmware that uses RAM as ROM or EPROM and provides control and monitoring and manipulation through the use of elementary and basic device functionality commands (machine code primitives) to accommodate the needs of polymorphic cipher engine software so that the software achieves the same results as thou it had access to programmable logic arrays, gate and logic blocks found in field programmable gate array chips.

## Claims

### Claim 1

A printed circuit board having at least one non field programmable gate array micro processor chip wherein said chip is configured using firmware such that a shared memory is created by a non-persisted memory mapping function, said shared memory being in the form of a look up table: wherein the transfer function of a circuit within a field programmable gate array chip is simulated by partitioning a sufficiently large amount of memory having memory addresses into different blocks corresponding to different circuits represented by the transfer function in a portion of the memory and wherein indexing to the memory addresses and using the contiguous memory for a look up table corresponds to loading a field programmable gate array chip and its internal fabric configuration as if it were a new circuit.

### Claim 2 (depends on 1)

The printed circuit board according to claim 1 wherein said shared memory comprises a sequence of digital signals that can be represented/implemented by a finite state machine.