# US 10,482,212 B2 · Automated resistance and capacitance extraction and netlist generation of logic cells

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- Number: US 10,482,212 B2
- Document ID: US10482212B2
- Status: Granted
- Kind: B2
- Application number: 15/901,749
- Filed: 2018-02-21
- Published: 2018-08-23
- Granted: 2019-11-19
- Earliest claimed: 2017-02-23
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Zudian Qin; Karim El Sayed; Victor Moroz; Xi-Wei Lin
- Web page: https://patentgrep.com/patent/US10482212B2

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/30: Circuit design
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 89/10: Integrated device layouts
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation. An annotated netlist is developed for the plurality of the transistors interconnects endpoints identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation.

## Claims

### Claim 1

A method for development of an integrated circuit fabrication process, the method comprising:
providing to a computer system a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design;
the computer system identifying, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout;
a computer system synthesizing by simulation of a fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout;
a computer system estimating, from the three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;
a computer system estimating, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design;
a computer system developing an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation;
writing the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values; and
applying the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.

### Claim 2 (depends on 1)

The method of claim 1, wherein identifying locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout comprises:
identifying a first one of the transistors in the layout; and
identifying gate, source and drain terminals of the first transistor in the layout; and
identifying locations of interconnect endpoints as X/Y coordinates of the gate, source and drain terminals of the first transistor.

### Claim 3 (depends on 2)

The method of claim 2, wherein identifying gate, source and drain terminals of the first transistor comprises:
identifying as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifying as the gate terminal of the first transistor, a region where a gate conductor geometry identified in the layout intersects the active region; and
identifying as the source and drain terminals of the first transistor, respective portions of the active region on longitudinally opposite sides of the gate region.

### Claim 4 (depends on 3)

The method of claim 3, further comprising naming the first transistor as a p-type transistor when the active region of the first transistor intersects an n-type well geometry identified in the layout.

### Claim 5 (depends on 3)

The method of claim 3, further comprising naming the first transistor as an n-type transistor when the active region of the first transistor does not intersect an n-type well geometry identified in the layout.

### Claim 6 (depends on 2)

The method of claim 2, wherein identifying gate, source and drain terminals of the first transistor comprises:
identifying as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifying as gate terminals of the first transistor, regions where a gate conductor geometry and a plurality of fin geometries identified in the layout intersect the active region; and
identifying as source and drain terminals of the first transistor, regions where the plurality of fin geometries intersect the active region, the source and drain terminals on longitudinally opposite sides of the gate terminals.

### Claim 7 (depends on 1)

The method of claim 1, wherein identifying locations for a plurality of interconnect endpoints in the layout comprises identifying pins from a plurality of pin geometries identified in the layout.

### Claim 8 (depends on 1)

The method of claim 1, wherein applying the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test comprises using the circuit simulator to estimate circuit timing.

### Claim 9 (depends on 1)

The method of claim 1, wherein applying the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test comprises using the circuit simulator to estimate power consumption.

### Claim 10 (depends on 1)

The method of claim 1, further comprising verifying designed circuit connectivity and functionality of the circuit design by:
removing the parasitic resistance values and the parasitic capacitance values from the annotated netlist, to develop a nominal netlist; and
verifying the designed circuit connectivity and functionality using the nominal netlist.

### Claim 11 (depends on 1)

The method of claim 1, further comprising, estimating, from the three-dimensional circuit representation, parasitic resistance values between each pair of the interconnect endpoints which share an interconnect.

### Claim 12 (depends on 1)

The method of claim 1, further comprising, estimating, from the three-dimensional circuit representation, parasitic capacitance values between each pair of the interconnect endpoints which are pins of the circuit design.

### Claim 13 (depends on 1)

The method of claim 1, wherein estimating parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect comprises simulating a current flow through the shared interconnect from one endpoint of the pair to the other endpoint of the pair in the three-dimensional circuit representation.

### Claim 14

A system for aiding development of an integrated circuit fabrication process, the system comprising a memory and a data processor coupled to the memory, the data processor configured with:
a source of a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor of the circuit design or a pin of the circuit design;
a source of a description of a fabrication process under test;
a layout identifier;
a fabrication process simulator;
a parasitic resistance and capacitance estimator;
a netlist annotator; and
a flow controller which is programmed to:
operate the layout identifier to identify, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout;
operate the fabrication process simulator to synthesize, by the fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout;
operate the parasitic resistance and capacitance estimator to estimate, from three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;
operate the parasitic resistance and capacitance estimator to estimate, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design;
operate the netlist annotator to develop an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance and parasitic capacitance values estimated from the three-dimensional circuit representation; and
write the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values for use by a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.

### Claim 15 (depends on 14)

The system of claim 14, wherein in identifying locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout, the system:
identifies a first one of the transistors in the layout; and
identifies gate, source and drain terminals of the first transistor in the layout; and
identifies locations of interconnect endpoints as X/Y coordinates of the gate, source and drain terminals of the first transistor.

### Claim 16 (depends on 15)

The system of claim 15, wherein in identifying gate, source and drain terminals of the first transistor, the system
identifies as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifies as the gate terminal of the first transistor, a region where a gate conductor geometry identified in the layout intersects the active region; and
identifies as the source and drain terminals of the first transistor, respective portions of the active region on longitudinally opposite sides of the gate region.

### Claim 17 (depends on 16)

The system of claim 16, wherein the system further names the first transistor as a p-type transistor when the active region of the first transistor intersects an n-type well geometry identified in the layout.

### Claim 18 (depends on 16)

The system of claim 16, wherein the system further names the first transistor as an n-type transistor when the active region of the first transistor does not intersect an n-type well geometry identified in the layout.

### Claim 19 (depends on 15)

The system of claim 15, wherein in identifying gate, source and drain terminals of the first transistor, the system:
identifies as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifies as gate terminals of the first transistor, regions where a gate conductor geometry and a plurality of fin geometries identified in the layout intersect the active region; and
identifies as source and drain terminals of the first transistor, regions where the plurality of fin geometries intersect the active region, the source and drain terminals on longitudinally opposite sides of the gate terminals.

### Claim 20 (depends on 14)

The system of claim 14, wherein in identifying locations for a plurality of interconnect endpoints in the layout, the system identifies pins from a plurality of pin geometries identified in the layout.

### Claim 21 (depends on 14)

The system of claim 14, wherein the system applies the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test by using the circuit simulator to estimate circuit timing.

### Claim 22 (depends on 14)

The system of claim 14, wherein the system applies the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test by using the circuit simulator to estimate power consumption.

### Claim 23 (depends on 14)

The system of claim 14, wherein in verifying designed circuit connectivity and functionality of the circuit design, the system:
removes the parasitic resistance values and the parasitic capacitance values from the annotated netlist, to develop a nominal netlist; and
verifies the designed circuit connectivity and functionality using the nominal netlist.

### Claim 24 (depends on 14)

The system of claim 14, wherein the system further estimates, from the three-dimensional circuit representation, parasitic resistance values between each pair of the interconnect endpoints which share an interconnect.

### Claim 25 (depends on 14)

The system of claim 14, wherein the system further estimates, from the three-dimensional circuit representation, parasitic capacitance values between each pair of the interconnect endpoints which are pins of the circuit design.

### Claim 26 (depends on 14)

The system of claim 14, wherein the system further estimates parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect comprises simulating a current flow through the shared interconnect from one endpoint of the pair to the other endpoint of the pair in the three-dimensional circuit representation.

### Claim 27

A non-transitory computer readable medium having stored thereon a plurality of instructions which when executed by a processor aids development of an integrated circuit fabrication process when provided with a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design, the plurality of instructions comprising instructions that cause the processor to:
identify, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout;
synthesize by simulation of a fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout;
estimate, from the three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;
estimate, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design;
develop an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation; and
write the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values for use by a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.

### Claim 28 (depends on 27)

The non-transitory computer readable medium of claim 27, wherein identifying locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout comprises:
identifying a first one of the transistors in the layout; and
identifying gate, source and drain terminals of the first transistor in the layout; and
identifying locations of interconnect endpoints as X/Y coordinates of the gate, source and drain terminals of the first transistor.

### Claim 29 (depends on 28)

The non-transitory computer readable medium of claim 28, wherein identifying gate, source and drain terminals of the first transistor comprises:
identifying as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifying as the gate terminal of the first transistor, a region where a gate conductor geometry identified in the layout intersects the active region; and
identifying as the source and drain terminals of the first transistor, respective portions of the active region on longitudinally opposite sides of the gate region.

### Claim 30 (depends on 29)

The non-transitory computer readable medium of claim 29, further comprising naming the first transistor as a p-type transistor when the active region of the first transistor intersects an n-type well geometry identified in the layout.

### Claim 31 (depends on 29)

The non-transitory computer readable medium of claim 29, further comprising naming the first transistor as an n-type transistor when the active region of the first transistor does not intersect an n-type well geometry identified in the layout.

### Claim 32 (depends on 28)

The non-transitory computer readable medium of claim 28, wherein identifying gate, source and drain terminals of the first transistor comprises:
identifying as an active region of the first transistor, a region where an active region geometry identified in the layout intersects a predetermined bounding box of the layout;
identifying as gate terminals of the first transistor, regions where a gate conductor geometry and a plurality of fin geometries identified in the layout intersect the active region; and
identifying as source and drain terminals of the first transistor, regions where the plurality of fin geometries intersect the active region, the source and drain terminals on longitudinally opposite sides of the gate terminals.

### Claim 33 (depends on 27)

The non-transitory computer readable medium of claim 27, wherein identifying locations for a plurality of interconnect endpoints in the layout comprises identifying pins from a plurality of pin geometries identified in the layout.

### Claim 34 (depends on 27)

The non-transitory computer readable medium of claim 27, wherein applying the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test comprises using the circuit simulator to estimate circuit timing.

### Claim 35 (depends on 27)

The non-transitory computer readable medium of claim 27, wherein applying the annotated netlist in a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test comprises using the circuit simulator to estimate power consumption.

### Claim 36 (depends on 27)

The non-transitory computer readable medium of claim 27, further comprising verifying designed circuit connectivity and functionality of the circuit design by:
removing the parasitic resistance values and the parasitic capacitance values from the annotated netlist, to develop a nominal netlist; and
verifying the designed circuit connectivity and functionality using the nominal netlist.

### Claim 37 (depends on 27)

The non-transitory computer readable medium of claim 27, further comprising, estimating, from the three-dimensional circuit representation, parasitic resistance values between each pair of the interconnect endpoints which share an interconnect.

### Claim 38 (depends on 27)

The non-transitory computer readable medium of claim 27, further comprising, estimating, from the three-dimensional circuit representation, parasitic capacitance values between each pair of the interconnect endpoints which are pins of the circuit design.

### Claim 39 (depends on 27)

The non-transitory computer readable medium of claim 27, wherein estimating parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect comprises simulating a current flow through the shared interconnect from one endpoint of the pair to the other endpoint of the pair in the three-dimensional circuit representation.