# US 10,482,209 B1 · Field programmable operation block array

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- Number: US 10,482,209 B1
- Document ID: US10482209B1
- Status: Granted
- Kind: B1
- Application number: 16/055,242
- Filed: 2018-08-06
- Granted: 2019-11-19
- Earliest claimed: 2018-08-06
- Assignees: HLS Logix LLC
- Applicants: HLS Logix LLC
- Inventors: Jason Daniel Gorski; Darrin Michael Hanna
- Web page: https://patentgrep.com/patent/US10482209B1

## CPC

- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- H03K 19/17708: {using an AND matrix followed by an OR matrix, i.e. programmable logic arrays}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A field-programmable operation array includes an interconnect network and a plurality of operation blocks, including a first operation block and a second operation block, electrically connected to the interconnect network. Each operation block includes an arithmetic logic unit and a plurality of logic gates. A pass signal output by the arithmetic logic unit of the first operation is received by the arithmetic logic unit of the second operation block.

## Claims

### Claim 1

A field programmable operation array comprising:
an interconnect network; and
a plurality of operation blocks, including a first operation block and a second operation block, electrically connected to the interconnect network,
wherein each operation block includes an arithmetic logic unit and a plurality of logic gates, and
wherein a pass signal output by the arithmetic logic unit of the first operation block is received by the arithmetic logic unit of the second operation block,
wherein each arithmetic logic unit is configured to receive two multi-bit inputs via the interconnect network, and wherein the pass signal is received by the arithmetic logic unit of the second operation block independent of the interconnect network,
wherein each arithmetic logic unit includes an AND gate, an OR gate, and an XOR gate configured to receive the two multi-bit inputs and output a multi-bit signal,
wherein each arithmetic logic unit includes an adder block configured to receive the two multi-bit inputs and output a multi-bit signal representing a sum of or difference between the two multi-bit inputs, and
wherein each arithmetic logic unit includes a comparison block configured to receive the two multi-bit inputs and output a comparison signal indicating that a first of the two multi-bit inputs is greater than, less than, or equal to a second of the two multi-bit inputs.

### Claim 2 (depends on 1)

The field programmable operation array of claim 1, wherein each arithmetic logic unit includes a first multiplexer electrically connected to the AND gate, the OR gate, the XOR gate, and the adder block.

### Claim 3 (depends on 2)

The field programmable operation array of claim 2, wherein each arithmetic logic unit includes a second multiplexer electrically connected to the comparison block.

### Claim 4 (depends on 3)

The field programmable operation array of claim 3, wherein the second multiplexer is configured to output the pass signal.

### Claim 5

An operation block for a field programmable operation array, the operation block comprising:
an arithmetic logic unit configured to output a pass signal to another operation block in the field programmable operation array; and
a plurality of logic gates including a first AND gate, a second AND gate, a first XOR gate, and a first OR gate,
wherein the arithmetic logic unit is configured to receive two multi-bit inputs via an interconnect network, and wherein the pass signal is output to another operation block independent of the interconnect network,
wherein the arithmetic logic unit includes a third AND gate, a second OR gate, and a second XOR gate configured to receive the two multi-bit inputs and output a multi-bit signal,
wherein the arithmetic logic unit includes an adder block configured to receive the two multi-bit inputs and output a multi-bit signal representing a sum of or difference between the two multi-bit inputs, and
wherein the arithmetic logic unit includes a comparison block configured to receive the two multi-bit inputs and output a comparison signal indicating that a first of the two multi-bit inputs is greater than, less than, or equal to a second of the two multi-bit inputs.

### Claim 6 (depends on 5)

The operation block of claim 5, wherein the arithmetic logic unit includes a first multiplexer electrically connected to the third AND gate, the second OR gate, the second XOR gate, and the adder block.

### Claim 7 (depends on 6)

The operation block of claim 6, wherein the arithmetic logic unit includes a second multiplexer electrically connected to the comparison block, wherein the second multiplexer is configured to output the pass signal.

### Claim 8 (depends on 5)

The operation block of claim 5, further comprising a plurality of flip-flops including a first flip-flop, a second flip-flop, and a third flip-flop.

### Claim 9 (depends on 8)

The operation block of claim 8, wherein the first flip-flop is electrically connected to an output of the second AND gate, the second flip-flop is electrically connected to an output of the first AND gate and the OR gate, and the third flip-flop is electrically connected to an output of the arithmetic logic unit.