# US 10,482,207 B2 · Verification support apparatus and design verification support method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,207 B2 - Document ID: US10482207B2 - Status: Granted - Kind: B2 - Application number: 15/984,545 - Filed: 2018-05-21 - Published: 2018-11-29 - Granted: 2019-11-19 - Earliest claimed: 2017-05-24 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Osamu Sugahara - Web page: https://patentgrep.com/patent/US10482207B2 ## CPC - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 30/3312: Timing analysis - G06F 30/396: Clock trees - G06F 2111/04: Constraint-based CAD - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A design verification support apparatus includes, a memory that stores circuit information and test pattern information, and a processor coupled to the memory. The processor performs a process including, acquiring the circuit information and the test pattern information from the memory, calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information, selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle, and calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a delay time. ## Claims ### Claim 1 A design verification support apparatus comprising: a memory configured to store circuit information including information on a connection destination of a component circuit included in a semiconductor having a scan chain, and a propagation delay occurring by the component circuit; and test pattern information indicating a test value to be input from a scan-in terminal of the scan chain at each cycle of a first clock signal output by a clock source; and a processor coupled to the memory, configured to perform a first processing of acquiring the circuit information and the test pattern information from the memory, calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information, and selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle; and a second processing of calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a first delay time calculated for the first memory circuit among delay times calculated for the plurality of memory circuits, respectively. ### Claim 2 (depends on 1) The design verification support apparatus according to claim 1, comprising: the processor configured to detect whether a first error occurs based on a comparison result obtained by comparing a scan-out value output from a scan-out terminal of the scan chain through the second processing with an expected value of the scan-out value. ### Claim 3 (depends on 1) The design verification support apparatus according to claim 1, comprising: the processor configured to calculate a signal polarity of the first clock signal when the first clock signal reaches each of the plurality of memory circuits, and then calculate the first output value of the first memory circuit when the second clock signal having the signal polarity is supplied to the first memory circuit. ### Claim 4 (depends on 1) The design verification support apparatus according to claim 1, comprising: the processor configured to detect, from the circuit information, a clock control circuit, which is included within a clock tree that propagates the first clock signal to a clock terminal of each of the plurality of memory circuits and controls propagation of the first clock signal to the clock terminal, and detect whether a second error occurs based on a determination result obtained by determining whether the clock control circuit has changed to a state in which propagation of the first clock signal to the clock terminal is stopped when the second processing is performed. ### Claim 5 (depends on 1) The design verification support apparatus according to claim 1, comprising: the processor configured to detect, from the circuit information, a first component circuit, which is included within a clock tree that propagates the first clock signal to a clock terminal of each of the plurality of memory circuits and does not affect the shift operation, calculate a second delay time occurring until the first clock signal reaches the first component circuit from the clock source, based on the circuit information, and calculate a change of a signal for the first component circuit when a third clock signal is supplied to the first component circuit when the second processing is performed, the third clock signal being obtained by delaying the first clock signal by the second delay time. ### Claim 6 (depends on 1) The design verification support apparatus according to claim 1, comprising: the processor configured to calculate respective output values of the plurality of memory circuits based on the second clock signal obtained by delaying the first clock signal by the delay time calculated for each of the plurality of memory circuits at other than the cycles at first two cycles and a last one cycle of the first clock signal in a scan shift operation section in which the shift operation is performed. ### Claim 7 A design verification support method performed by a computer coupled to a memory that stores circuit information including information on a connection destination of a component circuit included in a semiconductor having a scan chain, and a propagation delay occurring by the component circuit; and test pattern information indicating a test value to be input from a scan-in terminal of the scan chain at each cycle of a first clock signal output by a clock source, the design verification support method comprising: acquiring the circuit information and the test pattern information from the memory; calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information; selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle; and calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a first delay time calculated for the first memory circuit among delay times calculated for the plurality of memory circuits, respectively. ### Claim 8 A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process for design verification support, the computer coupled to a memory that stores circuit information including information on a connection destination of a component circuit included in a semiconductor having a scan chain, and a propagation delay occurring by the component circuit; and test pattern information indicating a test value to be input from a scan-in terminal of the scan chain at each cycle of a first clock signal output by a clock source, the process comprising: acquiring the circuit information and the test pattern information from the memory; calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information; selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle; and calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a first delay time calculated for the first memory circuit among delay times calculated for the plurality of memory circuits, respectively.