# US 10,482,205 B2 · Logic analyzer for integrated circuits

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- Number: US 10,482,205 B2
- Document ID: US10482205B2
- Status: Granted
- Kind: B2
- Application number: 15/658,086
- Filed: 2017-07-24
- Published: 2019-01-24
- Granted: 2019-11-19
- Earliest claimed: 2017-07-24
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Akhilesh Mahajan; Bokka Abhiram Sai Krishna; Keshava Gopal Goud Cheruku
- Web page: https://patentgrep.com/patent/US10482205B2

## CPC

- G06F 30/3312: Timing analysis
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G06F 11/25: Testing of logic operation, e.g. by logic analysers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Monitoring signals in an integrated circuit can include monitoring a probed signal of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit, detecting state changes in the probed signal using the logic analyzer circuit, and generating, within the logic analyzer circuit, a file specifying time stamped state changes of the probed signal.

## Claims

### Claim 1

A method for monitoring signals in an integrated circuit, comprising:
monitoring a probed signal within the integrated circuit using a logic analyzer circuit implemented within the integrated circuit;
detecting state changes in the probed signal using a trace circuitry in the logic analyzer circuit, wherein the trace circuitry is configured to receive the signal and determine whether a current state of the signal is different from a prior state of the signal;
generating, by a file generation circuit in the logic analyzer circuit coupled to the trace circuitry, ASCII encoded data specifying time stamped state changes of the probed signal, wherein the file generation circuit is configured to generate a file specifying the ASCII encoded data; and
providing the file, using an interface of the logic analyzer circuit coupled to the file generation circuit, to another circuit or system.

### Claim 2 (depends on 1)

The method of claim 1, wherein the file does not store continuously sampled values of the probed signal.

### Claim 3 (depends on 1)

The method of claim 1, wherein the file is specified as a value change dump file.

### Claim 4 (depends on 1)

The method of claim 1, wherein the providing comprises:
outputting the ASCII encoded data to an external system in substantially real time as generated.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
in response to determining that a state change of the probed signal corresponds to a trigger condition, initiating a predetermined action associated with the trigger condition.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
providing the ASCII encoded data to a processor within the integrated circuit, wherein the processor is configured to execute program code.

### Claim 7 (depends on 1)

The method of claim 1, wherein the providing comprises:
providing the ASCII encoded data to an external system, wherein the external system is configured to generate a visualization of the ASCII encoded data.

### Claim 8 (depends on 1)

The method of claim 1, wherein the file generation circuit generates the file by:
encoding a header section;
encoding a variable definition section;
encoding an initial value section; and
encoding a value change section.

### Claim 9 (depends on 1)

The method of claim 1, wherein the logic analyzer circuit is implemented in hardware using programmable circuitry of the integrated circuit.

### Claim 10

An integrated circuit, comprising:
monitored circuitry configured to generate a signal; and
a logic analyzer circuit configured to monitor the signal to detect state changes in the signal and generate ASCII encoded data specifying time stamped state changes of the signal, wherein the logic analyzer circuit comprises:
a trace circuitry configured to receive the signal and determine whether a current state of the signal is different from a prior state of the signal;
a file generation circuit coupled to the trace circuitry, wherein the file generation circuit is configured to generate a file specifying the ASCII encoded data; and
an interface coupled to the file generation circuit.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the file does not store continuously sampled values of the probed signal.

### Claim 12 (depends on 10)

The integrated circuit of claim 10, wherein the file is specified as a value change dump file.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, wherein the trace circuitry is configured to, in response to determining that a state change of the signal corresponds to a trigger condition, initiate a predetermined action associated with the trigger condition.

### Claim 14 (depends on 10)

The integrated circuit of claim 10, further comprising:
a processor coupled to the interface, wherein the processor is configured to execute program code and to receive the file.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the processor is configured to generate a waveform view of the signal from the file on an external system coupled to the integrated circuit.

### Claim 16 (depends on 10)

The integrated circuit of claim 10, further comprising:
an input/output circuit coupled to the interface, wherein the input/output circuit is configured to output the file to an external system.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the external system generates a waveform view of the signal from the file.

### Claim 18 (depends on 10)

The integrated circuit of claim 10, wherein the logic analyzer circuit is implemented in hardware using programmable circuitry of the integrated circuit.