# US 10,482,203 B2 · Method for simulating execution of an application on a multi-core processor

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- Number: US 10,482,203 B2
- Document ID: US10482203B2
- Status: Granted
- Kind: B2
- Application number: 16/043,784
- Filed: 2018-07-24
- Published: 2018-11-15
- Granted: 2019-11-19
- Earliest claimed: 2016-02-01
- Assignees: King Fahd University of Petroleum and Minerals
- Applicants: King Fahd University of Petroleum and Minerals
- Inventors: Muhammad Elnasir Elrabaa; Ayman Ali Hroub
- Web page: https://patentgrep.com/patent/US10482203B2

## CPC

- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F 11/3636: {by tracing the execution of the program}
- G06F 11/3648: {using additional hardware}
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 2115/10: Processors
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.

## Claims

### Claim 1

A computer-implemented method for simulating execution of an application on a many-core target machine, the method comprising:
acquiring, by a processor from a host processor of the computer communicatively coupled to the processor, a base clock per instruction (CPI) of a target machine being simulated, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, the processor including a plurality of processing cores communicatively coupled one to another via respective routers;
translating, by the host processor, the application of the target machine to a compact executable trace to be executed by the processor;
providing, by the host processor, the compact executable trace to the processor and executing the compact executable trace on the processor;
determining, by the processor, whether to adjust a simulation speed based on receiving a control signal from any of the routers;
adjusting dynamically, by the processor, an update rate of a global target clock counter (GTCC) that defines the simulation speed of the processor, the update rate being based on the CPI of the target machine;
acquiring one or more cache miss data frames and cache miss code frames from an off-chip memory controller communicatively coupled to the host processor and an off-chip memory module;
writing one or more replacement data frames and replacement code frames back to the off-chip memory from the off-chip memory module; and
providing, by the processor, simulation results to the host processor.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
profiling, by the host processor, each instruction of the target application to generate a profiled image of the application, the profiled image including an object for each unique instruction of the application, and wherein each instruction of the application is mapped to a unique address in the profiled image via a hash function.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
generating, by the host processor from the profiled image, instructions for the processor to execute.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
setting, by the processor, the update rate of the GTCC to an initial value that is based on the CPI and a number of host cycles required to execute a single instruction.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
reducing the simulation speed by half the initial value, based on a simulation speed controller (SSC) included in the processor, receiving the control signal; and
increasing the simulation speed twice the initial value based on the SSC not receiving the control signal in a predetermined amount of time.