Winograd algorithm on a matrix processing architecture

A method, comprising:

• receiving, by a matrix processing circuit, matrix data associated with a plurality of matrix multiplication operations, wherein:
• the matrix processing circuit comprises a plurality of memory resource blocks (MRBs) and a plurality of matrix processing units (MPUs), wherein the plurality of MPUs comprise circuitry to perform matrix multiplication;
• and
• the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each other;
• loading, by the matrix processing circuit, the matrix data into a first subset of the plurality of MRBs;
• extracting, by the matrix processing circuit, a plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs, wherein the plurality of matrix operands are extracted into a second subset of the plurality of MRBs, and wherein the plurality of matrix operands comprise an image matrix and the plurality of convolution filter matrices, wherein the image matrix is extracted from the image data and the plurality of convolution filter matrices are extracted from the interleaved convolution filter data;
• performing, by the matrix processing circuit, a first transform on the image matrix to obtain a transformed image matrix, wherein matrix multiplication of the transformed image matrix with each of the plurality of convolution filter matrices comprises fewer multiplication computations than matrix multiplication of the image matrix with each of the plurality of convolution filter matrices;
• causing, by the matrix processing circuit, the plurality of matrix multiplication operations to be performed by the plurality of MPUs, wherein the plurality of matrix multiplication operations comprise multiplying the transformed image matrix with each of the plurality of convolution filter matrices to produce a plurality of transformed matrix multiplication results;
• and
• performing, by the matrix processing circuit, a second transform on the plurality of transformed matrix multiplication results to obtain a plurality of final matrix multiplication results.

A system, comprising:

• a processor to execute a plurality of instructions associated with an application, wherein one or more of the plurality of instructions are associated with a plurality of matrix multiplication operations;
• and
• matrix processing circuitry to perform the plurality of matrix multiplication operations, wherein the matrix processing circuitry comprises:
• a plurality of memory resource blocks (MRBs);
• a plurality of matrix processing units (MPUs) comprising circuitry to perform matrix multiplication;
• and
• circuitry to:
• load matrix data associated with the plurality of matrix multiplication operations into a first subset of the plurality of MRBs, wherein the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each other;
• extract a plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs, wherein the plurality of matrix operands are extracted into a second subset of the plurality of MRBs, and wherein the plurality of matrix operands comprise an image matrix and the plurality of convolution filter matrices, wherein the image matrix is extracted from the image data and the plurality of convolution filter matrices are extracted from the interleaved convolution filter data;
• perform a first transform on the image matrix to obtain a transformed image matrix, wherein matrix multiplication of the transformed image matrix with each of the plurality of convolution filter matrices comprises fewer multiplication computations than matrix multiplication of the image matrix with each of the plurality of convolution filter matrices;
• cause the plurality of matrix multiplication operations to be performed by the plurality of MPUs, wherein the plurality of matrix multiplication operations comprise multiplying the transformed image matrix with each of the plurality of convolution filter matrices to produce a plurality of transformed matrix multiplication results;
• and
• perform a second transform on the plurality of transformed matrix multiplication results to obtain a plurality of final matrix multiplication results.

At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to:

• receive, by a matrix processing circuit, matrix data associated with a plurality of matrix multiplication operations, wherein:
• the matrix processing circuit comprises a plurality of memory resource blocks (MRBs) and a plurality of matrix processing units (MPUs), wherein the plurality of MPUs comprise circuitry to perform matrix multiplication;
• and
• the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each other;
• load, by the matrix processing circuit, the matrix data into a first subset of the plurality of MRBs;
• extract, by the matrix processing circuit, a plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs, wherein the plurality of matrix operands are extracted into a second subset of the plurality of MRBs, and wherein the plurality of matrix operands comprise an image matrix and the plurality of convolution filter matrices, wherein the image matrix is extracted from the image data and the plurality of convolution filter matrices are extracted from the interleaved convolution filter data;
• perform, by the matrix processing circuit, a first transform on the image matrix to obtain a transformed image matrix, wherein matrix multiplication of the transformed image matrix with each of the plurality of convolution filter matrices comprises fewer multiplication computations than matrix multiplication of the image matrix with each of the plurality of convolution filter matrices;
• cause, by the matrix processing circuit, the plurality of matrix multiplication operations to be performed by the plurality of MPUs, wherein the plurality of matrix multiplication operations comprise multiplying the transformed image matrix with each of the plurality of convolution filter matrices to produce a plurality of transformed matrix multiplication results;
• and
• perform, by the matrix processing circuit, a second transform on the plurality of transformed matrix multiplication results to obtain a plurality of final matrix multiplication results.