# US 10,482,054 B1 · AXI-CAPI adapter

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- Number: US 10,482,054 B1
- Document ID: US10482054B1
- Status: Granted
- Kind: B1
- Application number: 15/261,626
- Filed: 2016-09-09
- Granted: 2019-11-19
- Earliest claimed: 2016-09-09
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Ling Liu; Michaela Blott; Kimon Karras; Thomas Janson; Kornelis A. Vissers
- Web page: https://patentgrep.com/patent/US10482054B1

## CPC

- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G06F 13/4068: {Electrical coupling}
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H04L 49/9063: {Intermediate storage in different physical parts of a node or terminal}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

## Claims

### Claim 1

An Advanced eXtensible Interface (AXI) to coherent accelerator processor interface (CAPI) adapter, comprising:
a first signal interface configured to transfer CAPI signals between the adapter and a power service layer (PSL);
a second signal interface configured to transfer AXI signals between the adapter and an AXI-compatible accelerator; and
a hierarchy of hardware elements configured to convert the CAPI signals to at least two different types of AXI signals.

### Claim 2 (depends on 1)

The adapter of claim 1, wherein the at least two different types of AXI signals comprises at least two of: AXI Full signals, AXI Lite signals, and AXI Stream signals, and wherein the PSL is directly coupled to the first signal interface and the AXI-compatible accelerator is directly coupled to the second signal interface.

### Claim 3 (depends on 1)

The adapter of claim 1, wherein the hierarchy of hardware elements comprises a low-level shim coupled to the first signal interface and a high-level shim coupled to the low-level shim, wherein the high-level shim is configured to output AXI Stream signals based on the CAPI signals received by the low-level shim.

### Claim 4 (depends on 3)

The adapter of claim 3, wherein the hierarchy of hardware elements comprises an AXI Full module configured to output AXI Full signals based on receiving the AXI Stream signals from the high-level shim.

### Claim 5 (depends on 3)

The adapter of claim 3, wherein the hierarchy of hardware elements comprises an AXI Lite module coupled to the low-level shim, wherein the AXI Lite module is configured to output AXI Lite signals based on the CAPI signals received by the low-level shim.

### Claim 6 (depends on 3)

The adapter of claim 3, wherein the low-level shim comprises clock domain converter circuitry configured to convert the CAPI signals in a first clock domain to the AXI signals in a second clock domain.

### Claim 7 (depends on 1)

The adapter of claim 1, wherein the CAPI signals define (i) a task issued from a processor to the AXI-compatible accelerator and (ii) a pointer to a memory shared by the AXI-compatible accelerator and the processor containing data corresponding to the task.

### Claim 8

A field-programmable gate array (FPGA), comprising:
an Advanced eXtensible Interface (AXI)-compatible accelerator;
a power service layer (PSL) configured to transmit and receive coherent accelerator processor interface (CAPI) signals; and
an AXI-CAPI adapter coupled between the AXI-compatible accelerator and the PSL, wherein the AXI-CAPI adapter is configured to convert the CAPI signals received from the PSL to at least two different types of AXI signals and transmit the at least two different types of AXI signals to the AXI-compatible accelerator.

### Claim 9 (depends on 8)

The FPGA of claim 8, wherein the AXI-CAPI adapter comprises a hierarchy of hardware elements configured to convert the CAPI signals to the at least two different types of AXI signals.

### Claim 10 (depends on 9)

The FPGA of claim 9, wherein the at least two different types of AXI signals comprises at least two of: AXI Full signals, AXI Lite signals, and AXI Stream signals.

### Claim 11 (depends on 9)

The FPGA of claim 9, wherein the hierarchy of hardware elements comprises a low-level shim coupled to the PSL and a high-level shim coupled to the low-level shim, wherein the high-level shim is configured to output AXI Stream signals based on the CAPI signals received by the low-level shim.

### Claim 12 (depends on 11)

The FPGA of claim 11, wherein the hierarchy of hardware elements comprises an AXI Full module configured to output AXI Full signals based on receiving the AXI Stream signals from the high-level shim.

### Claim 13 (depends on 11)

The FPGA of claim 11, wherein the hierarchy of hardware elements comprises an AXI Lite module coupled to the low-level shim, wherein the AXI Lite module is configured to output AXI Lite signals based on the CAPI signals received by the low-level shim.

### Claim 14 (depends on 11)

The FPGA of claim 11, wherein the low-level shim comprises clock domain converter circuitry configured to convert the CAPI signals in a first clock domain to the AXI signals in a second clock domain.

### Claim 15 (depends on 8)

The FPGA of claim 8, wherein the CAPI signals define (i) a task issued from a processor external to the FPGA to the AXI-compatible accelerator and (ii) a pointer to a memory shared by the AXI-compatible accelerator and the processor containing data corresponding to the task.

### Claim 16

A method, comprising:
receiving coherent accelerator processor interface (CAPI) signals from a power service layer (PSL) at a first signal interface of an Advanced eXtensible Interface (AXI)-CAPI adapter;
converting the CAPI signals to at least two different types of AXI signals using a hierarchy of hardware elements in the AXI-CAPI adapter; and
transmitting the at least two different types of AXI signals on a second signal interface of the AXI-CAPI adapter, wherein the second signal interface is coupled to an AXI-compatible accelerator.

### Claim 17 (depends on 16)

The method of claim 16, wherein the at least two different types of AXI signals comprises at least two of: AXI Full signals, AXI Lite signals, and AXI Stream signals.

### Claim 18 (depends on 16)

The method of claim 16, wherein converting the CAPI signals to at least two different types of AXI signals comprises:
receiving the CAPI signals at a low-level shim in the AXI-CAPI adapter coupled to a high-level shim in the AXI-CAPI adapter; and
outputting AXI Stream signals from the high-level shim based on the CAPI signals received by the low-level shim.

### Claim 19 (depends on 18)

The method of claim 18, wherein converting the CAPI signals to at least two different types of AXI signals comprises:
receiving the AXI Stream signals at an AXI Full module in the AXI-CAPI adapter; and
outputting AXI Full signals from the AXI Full module based on the AXI Stream signals outputted by the high-level shim.

### Claim 20 (depends on 18)

The method of claim 18, wherein converting the CAPI signals to at least two different types of AXI signals:
outputting AXI memory mapped input/output (MMIO) signals from the low-level shim to an AXI Lite module in the AXI-CAPI adapter; and
converting the AXI MMIO signals into AXI Lite signals using the AXI Lite module.