# US 10,482,044 B2 · Computer, device control system, and device control method for direct memory access > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,044 B2 - Document ID: US10482044B2 - Status: Granted - Kind: B2 - Application number: 15/541,393 - Filed: 2016-01-15 - Published: 2018-01-25 - Granted: 2019-11-19 - Earliest claimed: 2015-01-16 - Assignees: NEC Corporation - Applicants: NEC Corporation - Inventors: Masahiko Takahashi - Web page: https://patentgrep.com/patent/US10482044B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/14: Handling requests for interconnection or transfer - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 15/17331: {Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]} - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract To realize DMA data transfer between a host computer and another computer even in the case that the host computer and the another computer are each equipped with a CPU, a memory, and so forth independently. A computer communicably connected with a first computer including a first memory and a driver for controlling a device, the computer comprising: the device; and a second memory, wherein a first DMA transfer is executed based on a DMA transfer request received from the driver, a second DMA transfer is executed to transfer data existing at a transfer destination address of the first DMA transfer between the first memory and the second memory, and the transfer destination address is detected as a result of executing the first DMA transfer. ## Claims ### Claim 1 A computer system comprising: a host computer that is communicably connected with a second computer, wherein the host computer includes a first memory and a driver for controlling a device of the second computer, the second computer includes a second memory, the host computer: executes a first direct memory access (DMA) transfer based on a DMA transfer request received from the driver, the first DMA transfer transferring data to a transfer destination address, executes a second DMA transfer to transfer data existing at the transfer destination address of the first memory to the second memory, and detects the transfer destination address as a result of executing the first DMA transfer, the second computer further comprises an input/output (I/O) memory management unit and a second driver, a record is recorded by a storage unit which the I/O memory management unit manages, the second driver acquires the transfer destination address by executing retrieval in the storage unit, and the second driver: requests the second DMA to transfer: receives an interrupt from the device when the second DMA is completed, and initiates a data transfer between the first memory and the second memory using receipt of the interrupt as a trigger. ### Claim 2 (depends on 1) The computer system according to claim 1, wherein the second driver transmits an interrupt, which is generated at a time of the data transfer, to the driver of the first computer. ### Claim 3 (depends on 1) The computer system according to claim 1, wherein the record further includes a transfer data size which is stored at the transfer destination address. ### Claim 4 (depends on 1) A device control system comprising: computer system according to claim 1; and the first computer, wherein the first computer and the computer are connected to each other so as to be able to communicate through a network. ### Claim 5 (depends on 4) The device control system according to claim 4, wherein the first computer and the computer are each equipped with an individual central processing unit (CPU). ### Claim 6 (depends on 4) The device control system according to claim 4, wherein the first computer includes a first bus extension unit, the computer includes a second bus extension unit, the first bus extension unit and the second bus extension unit are connected to each other through the network so as to be able to communicate, data relating to the DMA transfer between the driver and the device is converted into a packet by the first bus extension unit and the second bus extension unit, and transmission and reception of the packet is executed between the first bus extension unit and the second bus extension unit. ### Claim 7 (depends on 4) The device control system according to claim 4, wherein an interface of the network is PCI Express. ### Claim 8 A device control method comprising: executing, by a host computer, a first direct memory access (DMA) transfer based on a DMA transfer request received from a driver, the first DMA transfer transferring data to a transfer destination address, and executing, by the host computer, a second DMA transfer to transfer data existing at the transfer destination address of a first memory of the host computer to a second memory of a second computer, the transfer destination address being detected as a result of executing the first DMA transfer, wherein the host computer is communicably connected with the second computer, the host computer includes a first memory and a driver for controlling a device of the second computer, the second computer further comprises an input/output (I/O) memory management unit and a second driver, a record is recorded by a storage unit which the I/O memory management unit manages, the second driver acquires the transfer destination address by executing retrieval in the storage unit, and the second driver: requests the second DMA to transfer, receives an interrupt from the device when the second DMA is completed, and initiates a data transfer between the first memory and the second memory using receipt of the interrupt as a trigger. ### Claim 9 (depends on 1) The computer system according to claim 1, wherein the second driver transmits an interrupt to the driver of the first computer, is the interrupt being generated at a time of the data transfer between the first memory and the second memory. ### Claim 10 (depends on 2) The computer system according to claim 2, wherein the record further includes a transfer data size which is stored at the transfer destination address. ### Claim 11 (depends on 5) The device control system according to claim 5, wherein the first computer includes a first bus extension unit, the computer includes a second bus extension unit, and the first bus extension unit and the second bus extension unit are connected to each other through the network so as to be able to communicate, and data relating to the DMA transfer between the driver and the device is converted into a packet by the first bus extension unit and the second bus extension unit, and transmission and reception of the packet is executed between the first bus extension unit and the second bus extension unit. ### Claim 12 (depends on 5) The device control system according to claim 5, wherein an interface of the network is PCI Express. ### Claim 13 (depends on 6) The device control system according to claim 6, wherein an interface of the network is PCI Express.