# US 10,482,041 B2 · Read training a memory controller

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- Number: US 10,482,041 B2
- Document ID: US10482041B2
- Status: Granted
- Kind: B2
- Application number: 15/294,671
- Filed: 2016-10-14
- Published: 2017-02-02
- Granted: 2019-11-19
- Earliest claimed: 2013-09-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Tonia G. Morris; Jonathan C. Jasper; Arnaud J. Forestier
- Web page: https://patentgrep.com/patent/US10482041B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0673: {Single storage device}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4234: {being a memory bus}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

## Claims

### Claim 1

An integrated circuit device comprising:
a first interface to communicate with a memory controller over a bus interface and a second interface to communicate with one or more memory chips; and
memory module controller logic to:
receive a read command and a read identifier on a command and control signal line of the bus interface from the memory controller;
perform the read command to read data;
receive a grant signal after the receipt of the read command from the memory controller; and
in response to the grant signal, return the read data on a data line of the bus interface and send the received read identifier to the memory controller over a side band lane of the bus interface separate from the command and control signal line of the bus interface.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1 wherein the read identifier is looped back to the memory controller.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1 wherein the memory module controller logic is further to perform, in response to the receipt of a request from the memory controller, to enter a read identification training mode.

### Claim 4 (depends on 3)

The integrated circuit device of claim 3 wherein the memory module controller logic is further to:
receive a request from the memory controller to terminate the read identification training mode; and
terminate the read identification training mode.

### Claim 5

A system comprising:
a processor;
a memory module wherein the memory module comprises a memory module controller and a memory chip;
a bus interface; and
a memory controller wherein the memory controller is connected to the processor, wherein the memory module is connected to the memory controller through the bus interface, and wherein the memory module controller comprises memory module controller logic to:
receive a read command and a read identifier on a command and control signal line of the bus interface from the memory controller;
perform the read command to read data;
receive a grant signal following the receipt of the read command from the memory controller; and
in response to the grant signal, return the read data on a data line of the bus interface and send the received read identifier to the memory controller over a side band lane of the bus interface separate from the command and control signal line of the bus interface.

### Claim 6 (depends on 5)

The system of claim 5 wherein the read identifier is looped back to the memory controller.

### Claim 7 (depends on 5)

The system of claim 5 wherein the memory module controller logic is further to perform, in response to the receipt of a request from the memory controller to enter a read identification training mode.

### Claim 8 (depends on 7)

The system of claim 7 wherein the memory module controller logic is further to:
receive a request from the memory controller to terminate the read identification training mode; and
terminate the read identification training mode.