# US 10,482,040 B2 · Method, system, and apparatus for reducing processor latency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,040 B2 - Document ID: US10482040B2 - Status: Granted - Kind: B2 - Application number: 15/850,247 - Filed: 2017-12-21 - Published: 2019-06-27 - Granted: 2019-11-19 - Earliest claimed: 2017-12-21 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Shakti Kapoor - Web page: https://patentgrep.com/patent/US10482040B2 ## CPC - G06F 13/161: {with latency improvement} - G06F 3/061: {Improving I/O performance} - G06F 3/0622: {in relation to access} - G06F 3/064: {Management of blocks} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0888: using selective caching, e.g. bypass - G06F 13/1673: {using buffers} - G06F 2212/283: Plural cache memories - G06F 2212/6046: Using a specific cache allocation policy other than replacement policy - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed is a method, apparatus, and/or computer program product for reducing latency in a processor with regard to the execution of noncacheable operations that includes receiving noncacheable operations from one or both of the level 2 cache and a level 3 cache, sending the noncacheable operations to a noncacheable unit (NCU) associated with a core of the processor, executing the noncacheable operations by the NCU, and sending results of the executed noncacheable operations to a host bridge for output to an input/out device. The noncacheable operations bypass the core of the processor. ## Claims ### Claim 1 A method for reducing latency in a processor, the method comprising: receiving, at a coherent engine implemented in a level 2 subsystem of the processor, a source location, a data size, and a destination location; retrieving, by the coherent engine, data from the source location; sending, by the coherent engine, the data to a noncacheable unit (NCU) implemented in the level 2 subsystem and associated with a core of the processor to be output and bypassing the core resulting in reduced latency. ### Claim 2 (depends on 1) The method of claim 1, wherein the data is received in a plurality of operations, the method further comprising: buffering the data in a buffer; and sending complete data to the NCU. ### Claim 3 (depends on 1) The method of claim 1, further comprising: storing the source location in a first register of the coherent engine; and storing the destination location in a third register of the coherent engine. ### Claim 4 (depends on 3) The method of claim 3, further comprising storing the data size in a second register of the coherent engine. ### Claim 5 (depends on 1) The method of claim 1, wherein the source location is located in one of a level 2 cache and a level 3 cache. ### Claim 6 (depends on 1) The method of claim 1 wherein the destination location is located on an input/output peripheral. ### Claim 7 (depends on 1) The method of claim 1 further comprising sending the data to the destination location. ### Claim 8 A system for reducing latency in a processor, the system comprising: a non-cacheable unit (“NCU”) implemented in a level 2 subsystem of the processor and configured to perform non-cacheable operations, wherein the NCU is associated with a core of the processor; and a coherent engine implemented in the level 2 subsystem and configured to retrieve data from a source memory location and store it at a destination location bypassing the core resulting in reduced latency. ### Claim 9 (depends on 8) The system according to claim 8, wherein the coherent engine is further configured with a source register configured to store a source memory location address pointing to the source memory location and a destination register configured to store a destination memory location address pointing to the destination memory location. ### Claim 10 (depends on 9) The system according to claim 9 wherein the coherent engine is further configured with a data size register configured to store a size of data stored at the source memory location. ### Claim 11 (depends on 8) The system according to claim 8 wherein the non-cacheable unit is in communication with an input/output (“IO”) card, and wherein the destination memory location is on the IO card. ### Claim 12 (depends on 8) The system according to claim 8, further comprising a buffer configured to buffer data retrieved from the source memory location and to send complete data to the NCU. ### Claim 13 (depends on 8) The system according to claim 8, further comprising a level 2 cache, wherein the source memory location is in the level 2 cache. ### Claim 14 (depends on 13) The system according to claim 13, wherein the level 2 cache is in communication with a level 3 cache, and wherein the source memory location is in the level 3 cache. ### Claim 15 A computer readable medium comprising program code that, when executed, causes a coherent engine implemented in a level 2 subsystem of a processor to execute a method for reducing latency in the processor, wherein the method comprises: receiving a source location, a data size, and a destination location; retrieving data from the source location; sending the data to a noncacheable unit (NCU) implemented in the level 2 subsystem and associated with a core of the processor to be output and bypassing the core resulting in reduced latency. ### Claim 16 (depends on 15) The computer readable medium of claim 15, wherein the data is received in a plurality of operations, and wherein the method further comprises: buffering the data in a buffer; and sending complete data to the NCU. ### Claim 17 (depends on 15) The computer readable medium of claim 15, wherein the method further comprises: storing the source location in a source register of the coherent engine; and storing the destination location in a destination register of the coherent engine. ### Claim 18 (depends on 17) The computer readable medium of claim 17, wherein the method further comprises storing the data size in a data size register of the coherent engine. ### Claim 19 (depends on 15) The computer readable medium of claim 15, wherein the source location is located in one of a level 2 cache and a level 3 cache. ### Claim 20 (depends on 15) The computer readable medium of claim 15, wherein the destination location is located on an input/output peripheral, and wherein the method further comprises sending the data to the destination location.