# US 10,482,038 B2 · Programmable protocol independent bar memory for SSD controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,038 B2 - Document ID: US10482038B2 - Status: Granted - Kind: B2 - Application number: 15/219,210 - Filed: 2016-07-25 - Published: 2017-01-26 - Granted: 2019-11-19 - Earliest claimed: 2015-07-24 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Xianfeng Rui; Ka Wing Cheung; Ryan Yu; Ananthanarayanan Nagarajan - Web page: https://patentgrep.com/patent/US10482038B2 ## CPC - G06F 12/1425: {the protection being physical, e.g. cell, word, block} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 2212/1052: Security improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request. ## Claims ### Claim 1 A memory system, comprising: a programmable bit controller configured to define read-write properties to locations in a base address register (BAR) memory; a read-write switch configured to: receive a memory access request; identify whether the memory access request is a read access or a write access; and control routing of the memory access request for further processing based on the identify operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory; and an access controller configured to: receive the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access; determine a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access; bypass the write access when the read-write property is determined to be the first read-write property; and process the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the access controller is further configured to write 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and to write 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the access controller is further configured to calculate a destination address of the write access in the BAR memory. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter. ### Claim 6 A method, comprising: defining, with a programmable bit controller, read-write properties to locations in a base address register (BAR) memory; receiving, with a read-write switch, a memory access request; identifying, with the read-write switch, whether the memory access request is a read access or a write access; controlling, with the read-write switch, routing of the memory access request for further processing based on the identifying operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory; receiving, with an access controller, the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access; determining, with the access controller, a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access; bypass the write access when the read-write property is determined to be the first read-write property; and processing, with the access controller, the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties. ### Claim 7 (depends on 6) The method of claim 6, wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write. ### Claim 8 (depends on 7) The method of claim 7, further comprising writing 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and writing 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set. ### Claim 9 (depends on 6) The method of claim 6, further comprising calculating a destination address of the write access in the BAR memory. ### Claim 10 (depends on 6) The method of claim 6, wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter. ### Claim 11 A memory device, comprising: a programmable bit controller configured to define read-write properties to locations in a base address register (BAR) memory; a read-write switch configured to: receive a memory access request; identify whether the memory access request is a read access or a write access; and control routing of the memory access request for further processing based on the identify operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory; and an access controller configured to: receive the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access; determine a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access; bypass the write access when the read-write property is determined to be the first read-write property; and process the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write. ### Claim 13 (depends on 12) The memory device of claim 12, wherein the access controller is further configured to write 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and to write 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the controller is further configured to calculate a destination address of the write access in the BAR memory. ### Claim 15 (depends on 11) The memory device of claim 11, wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter.