# US 10,482,030 B2 · Methods of memory address verification and memory devices employing the same

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- Number: US 10,482,030 B2
- Document ID: US10482030B2
- Status: Granted
- Kind: B2
- Application number: 16/269,417
- Filed: 2019-02-06
- Published: 2019-06-06
- Granted: 2019-11-19
- Earliest claimed: 2017-08-25
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Alberto Troia
- Web page: https://patentgrep.com/patent/US10482030B2

## CPC

- G06F 12/1018: involving hashing techniques, e.g. inverted page tables
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G06F 3/061: {Improving I/O performance}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G11C 29/024: {in decoders}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 2029/1204: {Bit line control}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.

## Claims

### Claim 1

A memory device, comprising a memory controller configured to:
generate, for a data word to be stored at an address in a memory array, a location indicia corresponding to the address; and
send the data word and the location indicia to the memory array for storage.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory controller is further configured to:
command the memory array to read the data word from the address,
receive response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the memory controller is further configured to:
indicate an error if the location indicia of the response data does not correspond to the address.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the memory controller is further configured to:
output the data word if the location indicia of the response data corresponds to the address.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the memory controller is further configured to:
verify that a location indicia already stored at the address in the memory array corresponds to the address.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the location indicia is a hash of the address.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the address corresponds to a row of the memory array, and wherein the location indicia corresponds to the row.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the location indicia is the address.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the memory controller is configured to send the data word and the location indicia to the memory array for storage by appending or prepending the location indicia to the data word.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the data word comprises a plurality of bits.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the memory device comprises the memory array.

### Claim 12

A method of operating a memory device, comprising:
receiving a data word to be stored at an address in a memory array;
generating a location indicia corresponding to the address; and
sending the data word and the location indicia to the memory array for storage.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
commanding the memory array to read the data word from the address,
receiving response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
indicating an error if the location indicia of the response data does not correspond to the address.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
outputting the data word if the location indicia of the response data corresponds to the address.

### Claim 16 (depends on 12)

The method of claim 12, further comprising:
generating the location indicia by hashing the address.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
appending or prepending the location indicia to the data word before sending the data word and the location indicia to the memory array for storage.

### Claim 18

A memory system, comprising:
a host device; and
a memory device operatively coupled to the host device, the memory device configured to:
receive a data word to be stored at an address in a memory array;
generate a location indicia corresponding to the address; and
send the data word and the location indicia to the memory array for storage.

### Claim 19 (depends on 18)

The memory system of claim 18, wherein the memory device is further configured to:
commanding the memory array to read the data word from the address,
receiving response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.

### Claim 20 (depends on 18)

The memory system of claim 18, wherein the memory device comprises the memory array.