# US 10,482,028 B2 · Cache optimization for graphics systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,028 B2 - Document ID: US10482028B2 - Status: Granted - Kind: B2 - Application number: 15/493,757 - Filed: 2017-04-21 - Published: 2018-10-25 - Granted: 2019-11-19 - Earliest claimed: 2017-04-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Altug Koker; Balaji Vembu; Joydeep Ray; Abhishek R. Appu - Web page: https://patentgrep.com/patent/US10482028B2 ## CPC - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 12/023: {Free address space management} - G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning - G06T 1/60: Memory management - G06F 2212/1044: Space efficiency improvement - G06F 2212/1048: Scalability - G06F 2212/455: Image or video data - G06F 2212/604: Details relating to cache allocation - G06F 2212/608: Details relating to cache mapping - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes. ## Claims ### Claim 1 An apparatus comprising: one or more processors including a graphics processor, the one or more processors to: determine a type of each of one or more caches associated with the one or more processors; introduce cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches; upon detecting an invalidation for the one or more caches, implement and increment the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and facilitate replacement or re-allocation of locations of old cache coloring bits. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more processors to detect the type of the one or more caches including the one or more processors to detect read-only caches and read/write caches. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein for a detected cache that is a read-only cache, the one or more processors are further to track the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein for a detected cache that is a read/write cache, the one or more processors are further to track locations of old cache coloring bits and regard the locations as a miss. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the one or more processors are to define the cache coloring bits and associate the defined cache coloring bits with the one or more caches as part of a tag. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 7 A method comprising: detecting a type of each of one or more caches associated with one or more processors including a graphics processor; introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches; upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and facilitating replacement or re-allocation of locations of old cache coloring bits. ### Claim 8 (depends on 7) The method of claim 7, wherein detecting the type of each of the one or more caches including detecting read-only caches and read/write caches. ### Claim 9 (depends on 8) The method of claim 8, further comprising: for a detected cache that is a read-only cache, further comprising tracking the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable. ### Claim 10 (depends on 8) The method of claim 8, further comprising: for a detected cache that is a read/write cache, further comprising tracking locations of old cache coloring bits and regarding the locations as a miss. ### Claim 11 (depends on 7) The method of claim 7, further comprising defining the cache coloring bits and associating the defined cache coloring bits with the one or more caches as part of a tag. ### Claim 12 (depends on 7) The method of claim 7, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 13 At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising: detecting one or more caches associated with one or more processors including a graphics processor; introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches; upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and facilitating replacement or re-allocation of locations of old cache coloring bits. ### Claim 14 (depends on 13) The machine-readable medium of claim 13, wherein detecting the type of each of the one or more caches including detecting read-only caches and read/write caches. ### Claim 15 (depends on 14) The machine-readable medium of claim 14, further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising: for a detected cache that is a read-only cache, tracking the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable. ### Claim 16 (depends on 14) The machine-readable medium of claim 14, further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising: for a detected cache that is a read/write cache, tracking locations of old cache coloring bits and regarding the locations as a miss. ### Claim 17 (depends on 13) The machine-readable medium of claim 13, further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising: defining the cache coloring bits and associating the defined cache coloring bits with the one or more caches as part of a tag. ### Claim 18 (depends on 13) The machine-readable medium of claim 13, wherein the graphics processor is co-located with an application processor on a common semiconductor package.