# US 10,482,017 B2 · Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,017 B2 - Document ID: US10482017B2 - Status: Granted - Kind: B2 - Application number: 15/721,223 - Filed: 2017-09-29 - Published: 2019-04-04 - Granted: 2019-11-19 - Earliest claimed: 2017-09-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Karl I. Taht; Christopher B. Wilkerson; Ren Wang; James J. Greensky - Web page: https://patentgrep.com/patent/US10482017B2 ## CPC - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/0862: with prefetch - G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches} - G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel - G06F 2212/1021: Hit rate improvement - G06F 2212/282: Partitioned cache - G06F 2212/6028: Prefetching based on hints or prefetch instructions - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period. ## Claims ### Claim 1 A processor comprising: a cache; cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses, the cache controller circuitry further to receive a request to access a memory address and responsively determine one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses; cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period. ### Claim 2 (depends on 1) The processor of claim 1, further comprising a plurality of machine specific registers (MSRs) to store the one or more control addresses, the cache policies, and the partition-specific statistics. ### Claim 3 (depends on 1) The processor of claim 1, wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses. ### Claim 4 (depends on 1) The processor of claim 1, wherein a mask is applied to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses. ### Claim 5 (depends on 4) The processor of claim 4, wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set. ### Claim 6 (depends on 1) The processor of claim 1, wherein the cache policies comprise cache replacement policies. ### Claim 7 (depends on 1) The processor of claim 1, wherein the cache policies comprise cache line prefetch policies. ### Claim 8 (depends on 1) The processor of claim 1, wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition. ### Claim 9 A method comprising: partitioning, by cache controller circuitry, a processor cache into a plurality of cache partitions based on one or more control addresses; receiving, by the cache controller circuitry, a request to access a memory address and responsively determining one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses; applying, by cache policy assignment circuitry, different cache policies to different subsets of the plurality of cache partitions; and tracking, by cache performance monitoring circuitry, cache events for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period. ### Claim 10 (depends on 9) The method of claim 9, wherein the one or more control addresses, the cache policies, and the partition-specific statistics are stored in a plurality of machine specific registers (MSRs). ### Claim 11 (depends on 9) The method of claim 9, wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses. ### Claim 12 (depends on 9) The method of claim 9, further comprising applying a mask to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses. ### Claim 13 (depends on 12) The method of claim 12, wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set. ### Claim 14 (depends on 9) The method of claim 9, wherein the cache policies comprise cache replacement policies. ### Claim 15 (depends on 9) The method of claim 9, wherein the cache policies comprise cache line prefetch policies. ### Claim 16 (depends on 9) The method of claim 9, wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition. ### Claim 17 A system comprising: a memory; a processor comprising: a plurality of cores; a cache shared by the plurality of cores; cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses, the cache controller circuitry further to receive a request to access a memory address and responsively determine one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses; cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period. ### Claim 18 (depends on 17) The system of claim 17, further comprising a plurality of machine specific registers (MSRs) to store the control address, the cache policies, and the partition-specific statistics. ### Claim 19 (depends on 17) The system of claim 17, wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses. ### Claim 20 (depends on 17) The system of claim 17, wherein a mask is applied to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses. ### Claim 21 (depends on 20) The system of claim 20, wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set. ### Claim 22 (depends on 17) The system of claim 17, wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition.