# US 10,482,011 B2 · Method for managing a memory apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,482,011 B2 - Document ID: US10482011B2 - Status: Granted - Kind: B2 - Application number: 15/642,295 - Filed: 2017-07-05 - Published: 2017-10-19 - Granted: 2019-11-19 - Earliest claimed: 2008-11-06 - Assignees: Silicon Motion, Inc. - Applicants: Silicon Motion Inc. - Inventors: Tsai-Cheng Lin; Chun-Kun Lee - Web page: https://patentgrep.com/patent/US10482011B2 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 2212/7207: management of metadata or control data - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory apparatus includes at least one non-volatile memory element, which includes a plurality of physical blocks. A method for managing the memory apparatus includes: obtaining a first host address from a received first access command; linking the first host address to a first page of the physical block; obtaining a second host address from a received second access command; linking the second host address to a second page of the physical block; and selectively erasing a portion of the blocks according to a valid/invalid page count of the physical block corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block. ## Claims ### Claim 1 A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element comprising a plurality of physical blocks, and a processing unit, the method being performed by the processing unit and comprising: providing a plurality of blocks of the memory apparatus with a plurality of local page address linking tables within the memory apparatus, respectively, wherein each local page address linking table includes a plurality of entries, each entry of the plurality of entries being a logical address, the local page address linking tables comprise linking relationships between a plurality of physical page addresses of the blocks and a plurality of logical page addresses; and building a global page address linking table according to the local page address linking tables. ### Claim 2 (depends on 1) The method of claim 1, wherein the step of providing a plurality of blocks of the memory apparatus with a plurality of local page address linking tables further comprises: building a temporary local page address linking table for the local page address linking tables corresponding to programming/writing operations of the memory apparatus. ### Claim 3 (depends on 2) The method of claim 2, wherein each local page address linking table is built when at least a data page in the block has been programmed. ### Claim 4 (depends on 2) The method of claim 2, wherein each local page address linking table is built when all data pages in the block has been programmed. ### Claim 5 (depends on 2) The method of claim 2, wherein each local page address linking table is positioned in a predetermined page of the block. ### Claim 6 (depends on 5) The method of claim 5, wherein the step of building the global page address linking table of the memory apparatus according to the local page address linking table further comprises: reading one of the local page address linking tables to update the global page address linking table. ### Claim 7 (depends on 1) The method of claim 1, wherein the step of building the global page address linking table of the memory apparatus according to the local page address linking table further comprises: reading each of the local page address linking tables to build the global page address linking table. ### Claim 8 (depends on 1) The method of claim 1, wherein the ranking of a field of the global page address linking table represents a logical page address, and the content of the field represents an associated physical page address. ### Claim 9 (depends on 1) The method of claim 1, wherein a range of the logical page addresses in the local page address linking table is greater than a number of pages in the block. ### Claim 10 (depends on 1) The method for managing a memory apparatus of claim 1, wherein the plurality of blocks are logically divided into a data region and a spare region, and the step of the local page address linking tables comprise linking relationships between a plurality of physical page addresses of the blocks and a plurality of logical page addresses comprises: obtaining a first host address and first data from a received first access command; linking the first host address to a physical block belonging to the data region; obtaining a second host address and second data from a received second access command; and linking the second host address to the physical block; wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block. ### Claim 11 (depends on 10) The method of claim 10, further comprising: storing the first data into at least a first page of the physical block; and storing the second data into at least a second page of the physical block, wherein the second page of the physical block is next to the first page of the physical block. ### Claim 12 (depends on 10) The method of claim 10, wherein the first host address is linked to at least a first page of the physical block, and the second host address is linked to at least a second page of the physical block. ### Claim 13 (depends on 1) The method for managing a memory apparatus of claim 1, wherein the plurality of blocks are logically divided into a data region and a spare region, and the step of the local page address linking tables comprise linking relationships between a plurality of physical page addresses of the blocks and a plurality of logical page addresses comprises: obtaining a first host address and first data from a received first access command; linking the first host address to at least a page of a first physical block belonging to the data region; obtaining a second host address and second data from a received second access command; and linking the second host address to at least a page of a second physical block belonging to the data region, wherein the second physical block is different from the first physical block; wherein a difference value of the first host address and the second host address is smaller than a number of pages of each physical block. ### Claim 14 (depends on 13) The method of claim 13, further comprising: storing the first data into the first physical block; and storing the second data into the second physical block. ### Claim 15 (depends on 13) The method of claim 13, wherein the first host address is linked to at least a first page of the first physical block, and the second host address is linked to at least a second page of the second physical block. ### Claim 16 A memory apparatus, comprising: at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks; and a processing unit arranged to manage the memory apparatus according to a program code embedded in the processing unit or received from outside the processing unit, wherein the processing unit is arranged to provide a plurality of blocks of the memory apparatus with a plurality of local page address linking tables within the memory apparatus, respectively, each local page address linking table including a plurality of entries, each entry of the plurality of entries being a logical address, and the local page address linking tables comprise linking relationships between a plurality of physical page addresses of the blocks and a plurality of logical page addresses; wherein the processing unit is arranged to build the global page address linking table of the memory apparatus according to the local page address linking tables. ### Claim 17 (depends on 16) The memory apparatus of claim 16, wherein the processing unit builds a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus. ### Claim 18 (depends on 17) The memory apparatus of claim 17, wherein the local page address linking table is built when at least a data page in the block has been programmed. ### Claim 19 (depends on 17) The memory apparatus of claim 17, wherein the local page address linking table is built when all data pages in the block have been programmed. ### Claim 20 (depends on 16) The memory apparatus of claim 16, wherein the local page address linking table is positioned in the block. ### Claim 21 (depends on 20) The memory apparatus of claim 20, wherein the processing unit stores the local page address linking table into the last page of the block. ### Claim 22 (depends on 21) The memory apparatus of claim 21, wherein the processing unit reads one of the local page address linking tables to update the global page address linking table. ### Claim 23 (depends on 16) The memory apparatus of claim 16, wherein the processing unit reads each of the local page address linking tables to build the global page address linking table. ### Claim 24 (depends on 16) The memory apparatus of claim 16, wherein the ranking of a field of the global page address linking table represents a logical page address, and the content of the field represents an associated physical page address. ### Claim 25 (depends on 16) The memory apparatus of claim 16, wherein a range of the logical page addresses in the local page address linking table is greater than a number of pages in the block.