# US 10,481,991 B2 · Efficient testing of direct memory address translation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,991 B2 - Document ID: US10481991B2 - Status: Granted - Kind: B2 - Application number: 16/141,971 - Filed: 2018-09-26 - Published: 2019-02-14 - Granted: 2019-11-19 - Earliest claimed: 2017-08-12 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Manoj Dusanapudi; Shakti Kapoor; Nelson Wu - Web page: https://patentgrep.com/patent/US10481991B2 ## CPC - G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)} - G06F 11/2205: {using arrangements specific to the hardware being tested} - G06F 11/2221: {to test input/output devices or peripheral units} - G06F 11/26: Functional testing - G06F 11/2635: {using a storage for the test inputs, e.g. test ROM, script files} - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 13/102: {where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52)} - G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)} - G06F 2212/1016: Performance improvement - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input. ## Claims ### Claim 1 A computer-implemented method of testing an integrated circuit, the method comprising: loading a first translation table with a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit; and testing all the translation entries in the translation table by randomly selecting an entry of the table with translation information to run multiple consecutive tests of address translation. ### Claim 2 (depends on 1) The method of claim 1 further comprising; providing a random signal on an input of a multiplexer; selecting the random signal using a select input to the multiplexer; and providing the random signal from the multiplexer to the translation table to randomly select an entry of a translation control entry table during the test mode. ### Claim 3 (depends on 2) The method of claim 2 wherein the random signal is four bits and the translation table contains sixteen entries. ### Claim 4 (depends on 1) The method of claim 1 wherein the first translation table is a translation validation table (TVT) which contains translation validation entries for each of the plurality of agents that point to a translation control entry table. ### Claim 5 (depends on 4) The method of claim 4 wherein the translation validation entries comprise a translation table address (TTA), translation control entry tree depth, translation control entry table size and input/output page size. ### Claim 6 (depends on 1) The method of claim 1 wherein the plurality of agents comprises a central processing unit and at least one graphics processing unit. ### Claim 7 (depends on 1) The method of claim 1 wherein the method is performed by a link processing unit on an integrated circuit. ### Claim 8 (depends on 7) The method of claim 7 wherein the link processing unit is fabricated on the integrated circuit with a central processing unit. ### Claim 9 A computer-implemented method of testing a link processing unit on an integrated circuit, the method comprising: loading a first translation table with a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit, wherein the plurality of agents comprise a central processing unit and at least one graphics processing unit; testing all the translation entries in the translation table by randomly selecting an entry of the table with translation information to run multiple consecutive tests of address translation; providing a random signal on an input of a multiplexer; selecting the random signal using a select input to the multiplexer; and providing the random signal from the multiplexer to the translation table to randomly select an entry of a translation control entry table during the test mode. ### Claim 10 (depends on 9) The method of claim 9 wherein the translation table is a translation validation table (TVT) containing translation validation entries for each of the plurality of agents. ### Claim 11 (depends on 10) The method of claim 10 wherein the translation validation entries comprise a translation table address (TTA), translation control entry tree depth, translation control entry table size and input/output page size. ### Claim 12 A computer-implemented method of testing an integrated circuit, the method comprising: loading a first translation table with a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit; and using at least one agent of the plurality of agents connected to the integrated circuit in a test mode to test the translation entries in the translation table by randomly selecting an entry of the table with translation information to run multiple consecutive tests of address translation using the at least one agent. ### Claim 13 (depends on 12) The method of claim 12 further comprising; providing a random signal on an input of a multiplexer; selecting the random signal using a select input to the multiplexer; and providing the random signal from the multiplexer to the translation table to randomly select an entry of a translation control entry table during the test mode. ### Claim 14 (depends on 13) The method of claim 13 wherein the random signal is four bits and the translation table contains sixteen entries. ### Claim 15 (depends on 12) The method of claim 12 wherein the first translation table is a translation validation table (TVT) which contains translation validation entries for each of the plurality of agents that point to a translation control entry table. ### Claim 16 (depends on 15) The method of claim 15 wherein the translation validation entries comprise a translation table address (TTA), translation control entry tree depth, translation control entry table size and input/output page size. ### Claim 17 (depends on 12) The method of claim 12 wherein the plurality of agents comprises a central processing unit and at least one graphics processing unit. ### Claim 18 (depends on 12) The method of claim 12 wherein the method is performed by a link processing unit on an integrated circuit. ### Claim 19 (depends on 18) The method of claim 18 wherein the link processing unit is fabricated on the integrated circuit with a central processing unit.