# US 10,481,965 B2 · Method and apparatus for determining status element total with sequentially coupled counting status circuits

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- Number: US 10,481,965 B2
- Document ID: US10481965B2
- Status: Granted
- Kind: B2
- Application number: 15/389,238
- Filed: 2016-12-22
- Published: 2017-04-13
- Granted: 2019-11-19
- Earliest claimed: 2013-03-11
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Yih-Shan Yang; Shou-Nan Hung; Chun-Hsiung Hung; Yao-Jen Kuo; Meng-Fan Chang
- Web page: https://patentgrep.com/patent/US10481965B2

## CPC

- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection}
- G06F 11/08: Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 29/022: {in I/O circuitry}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 2216/14: Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

## Claims

### Claim 1

A circuit for counting status of page buffer outputs, comprising:
a plurality of status circuits to indicate status of a count of the status of page buffer outputs, the plurality of status circuits having inputs and outputs electrically coupled in series in a sequential order, wherein at least one status circuit in the plurality of status circuits comprises:
an upper latch to store a count status, and including a first end and a second end, the upper latch configured to store an initial count status corresponding to pass or fail status from a corresponding output of a page buffer; and
a pass gate connected between the input and the output of the status circuit, the pass gate including two switches having control gates connected to the first end and the second end respectively of the upper latch.

### Claim 2 (depends on 1)

The circuit of claim 1, the at least one status circuit further comprises:
a transistor connected to the output of the at least one status circuit, the transistor having a control gate, which is connected to one of the first and second ends of the upper latch, wherein the transistor is activated while a signal representing the count status corresponding to the fail status is received from the upper latch, and when activated passes the fail status to the output of the at least one status circuit.

### Claim 3 (depends on 1)

The circuit of claim 1, further comprising:
a lower latch coupled to the input of the at least one status circuit, wherein the lower latch is flipped in response to an input signal on the input of the at least one status circuit and a first control signal.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the upper latch is flipped in response to a signal of the lower latch and a second control signal when the upper latch stores fail status.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the first control signal precedes the second control signal.

### Claim 6 (depends on 1)

The circuit of claim 1, including:
control logic causing processing of the plurality of status circuits in the sequential order to count status circuits storing initial fail status.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein said processing of the plurality of status circuits in the sequential order, is interrupted from proceeding further in the sequential order, by one of the plurality of status circuits storing the count status corresponding to the fail status having not been counted in the total of the plurality of status circuits.

### Claim 8 (depends on 7)

The circuit of claim 7, wherein the control logic causes repetition of said processing of the plurality of status circuits in the sequential order, at least until none of the plurality of status circuits indicates that the count status corresponding to the fail status has not been counted.

### Claim 9 (depends on 6)

The circuit of claim 6, wherein said processing of the plurality of status circuits in the sequential order, is successful in proceeding through all of the sequential order, responsive to none of the plurality of status circuits storing the initial count status corresponding to the fail status.

### Claim 10 (depends on 1)

The circuit of claim 1, further comprising:
a page buffer with a plurality of page buffer outputs providing pass or fail statuses of a plurality of bit lines to the upper latches of the plurality of status circuits, the pass or fail statuses indicating one of at least pass and fail status of corresponding ones of the plurality of bit lines.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein an initial count status of the at least one count status circuit is determined by a corresponding page buffer output of the page buffer.

### Claim 12

An operation method of a fail bit count, comprising:
processing a plurality of status circuits in a sequential order to determine a count of bits having one of pass and fail status;
storing an initial count status in response to said one of pass and fail status in an upper latch in status circuits of the plurality of status circuits, the upper latch including a first end and a second end;
indicating, with a pass gate in of the plurality of status circuits including two switches having control gates connected to the first end and the second end respectively of the upper latch, whether the initial count status has been counted in the plurality of status circuits; and
on condition that the initial count status stored in the upper latch corresponds to the fail status, flipping the initial count status using a lower latch which is electrically coupled to an input of the status circuit to receive an output from a previous status circuit in the sequential order.

### Claim 13 (depends on 12)

The method of claim 12, wherein before the step of flipping the initial count status, turning off the two switches of the pass gate.

### Claim 14 (depends on 12)

The method of claim 12, wherein the status circuits further comprises:
a transistor connected to an output of the status circuits, the transistor having a control gate, which is connected to the upper latch, wherein the transistor is activated while a signal representing the fail status is stored in the upper latch, and including:
passing the fail status to an output of the status circuits using the transistor.